1. Preliminary measurements for the 8 channel prototype of SPD discriminator ASIC I.The 8 channel prototype. II.Status of the test. III.Noise. IV.Gain. V.Test plan. VI.Schedule for PRR and production. LHCb Calo Electronics Meeting – December 2003 – Clermont-Ferrand

2. I. The 8 channel prototype (I). integration.Random signal shape (20-30 phe/MIP): shaping methods discarded  integration. Dual channel: synchronous system + Pile-up correctionOnly about 80% of signal in 25 ns (no dead time for integration allowed) + response to consecutive events  Dual channel: synchronous system + Pile-up correction PMT gain limited by aging (DC current)  100fC/MIP in hotest cells. 5-10 MIP range to perform tail correction. Robust to temperature variations (band gap reference). Small cavity  Power consumption < 1W. Prototype at 3.3V (0.6 W)

3. I. The 8 channel prototype (II). Area: 30 mm 2. Package: naked die (10), JLCC68 (10) and EDQUAD TQFP 64 (30). Target package is EDQUAD TQFP 64 for size and power dissipation. Ceramic JLCC68 is also requested because better knowledge of its performance (used for previous prototypes).

4. II. Status of the test. 10 JLCC + 10 naked dies were receive at beginning of November. 46 EDQUAD TQFP were received last week. Automated test system is under development. Hardware (test boards and VHDL code for FPGA used for DAQ) is finished. Software (Labview and C) for data taking and on-line analysis is almost finished. Digital interface has been completely tested with random sequences write/read and is fully functional. Power consumption is as expected: 180 mA (0.6 W). Consumption of different supply pins is in agreement with simulation. Some further “manual” measurements have been done.

5. III. Noise (I): 50  PMT load (input resistor). Sigma of differential histogram between 1 and 2 mV r.m.s. Measurement error is not negligible compared with transition width. Possible contributions of pick-up noise should be studied.

6. III. Noise (II): 390  PMT load (input resistor). Sigma of differential histogram between 1 and 2 mV r.m.s. Noise increase is not seen. Measurement error is not negligible compared with transition width. Possible contributions of pick-up noise should be studied.

7. IV. Gain (I): pulse injection. A step pulse is differentiated through a series capacitor: the charge over RLPMT must be Q=Cac x Vstep (Vstep is the pulse amplitude). The pulse must be much longer than 25ns The time constant of the circuit <<25ns to inject all the charge in 1 period. The 95 % of the signal is on 25 ns (gain has been corrected).

8. IV. Gain (II): results. Gain for 390  PMT load : 1mV/fC. Linear range   1 pC of input charge or  1 V of threshold. Input referred noise (ENC) between 1 and 2 fC. MIP signal between 100 fC and 50 fC (after first compensation of PMT non-uniformities).

9. V. Test plan. 1.Offset per subchannel (function of pile-up compensation subtractor). 2.Noise per subchannel (function of pile-up compensation subtractor and PMT load). 3.Cross-talk between subchannel threshold (same Vref). 4.Low frequency noise (random trigger vs. sync. trigger). 5.Linearity (function of pile-up compensation subtractor). 6.Matching and calibration of of pile-up compensation. 7.Cross-talk between channels. 8.Pedestal stability with time. 9.Aging. 10.Tª dependence. 11.ESD test on inputs and control pins. 12.Possible effects of pick-up noise cause by massive switching of digital outputs (PCB dependent).

10. VI. Schedule. If no serious troubles are found systematic measurements might be finished by end of January 2004. When should we ask to pass the PRR? If no defects are find and PRR is passed on February chip will be ready for production in March? According to CMP it is possible “start production when you want”, different from a MPW run. Sharing production masks with PS VFE chip might save some money... It has been asked to CMP/AMS. Are the schedules for both chips compatible?