1. 1/8/2007 - L3 Data Path DesignCopyright 2006 - Joanne DeGroat, ECE, OSU1 ALUs and Data Paths Subtitle: How to design the data path of a processor.

2. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU2 Lecture overview  General Data Path Design  Design of a multifunction ALU

3. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU3 Design of ALUs and Data Paths  Objective: Design a General Purpose Data Path such as the datapath found in a typical computer.  A Data Path Contains: Registers – general purpose, special purpose Execution Units capable of multiple functions

4. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU4 ALU Operations (integer ALU)  Add(A+B)  Add with Carry(A+B+Cin)  Subtract(A-B)  Subtract with Borrow (A-B-Cin)  [Subract reverse (B-A)]  [Subract reverse with Borrow (B-A-Cin)]  Negative A (-A)  Negative B (-B)  Increment A (A+1)  Increment B (B+1)  Decrement A (A-1)  Decrement B (B-1)  Logical AND  Logical OR  Logical XOR  Not A  Not B  A  B  Multiply Step or Multiply  Divide Step or Divide  Mask  Conditional AND/OR (uses Mask)  Shift  Zero

5. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU5 A High Level Design From Hayes textbook on architecture.

6. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU6 The AMD 2901 Bit Slice ALU

7. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU7 The Architecture

8. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU8 Arithmetic Logic Circuits  The Brute Force Approach  A more modern approach

9. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU9 Arithmetic Logic Circuits  The Brute Force Approach Simple and straightfoward  A more modern approach

10. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU10 Arithmetic Logic Circuits  The Brute Force Approach  A more modern approach Where the logic unit and the adder unit are optimized

11. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU11 A Generic Function Unit  Another Design – a multifunction unit  Desire a generic functional unit that can perform many functions  A 4-to-1 mux will perform all basic logic functions of 2 inputs

12. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU12 Low level implementation At the implementation Level the design can be With transmission gates Very important for VLSI implementation Implementation has a total Of 16 transistors. Could also use NAND NOR implementation.

13. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU13 Low level implementation  An implementation in pass gates (CMOS)  When the control signal is a ‘1’ the value will be transmitted  Otherwise it is an open switch

14. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU14 Lets look at Binary Addition  We can use this generic function unit construct a generic ALU.  For Binary Addition consider the following: SUM i = A i xor B i xor C i C i+1 = A i B i + A i C i + B i C i

15. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU15 An Alternative - Define two signals  Equations for P and K  P i = A i xor B i  K i = A i ’ B i ’  Now can reform Sum, Cout equations into functions of P and K and Cin

16. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU16 New functions  Using these definitions of P and K  SUM i = P i xor C i  C i+1 = P i C i + P i ’ K i ’  = P i C i + A i B i  You can use the generic functional blocks to generate P and K and then select the correct function for final output

17. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU17 A bit slice of the ALU  Slice starts out with a generic unit which can produce any function of inputs A i and B i to produce P i  Need another to produce K i (kill block)  And a 3 rd to generate the result (results generator block)  And also need a dedicated unit to compute the carry out, the C i+1 term

18. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU18 Generation of the carry out  C i+1 = P i C i + P i ’K i ’  The carry chain is the critical path for arithmetic operations.  A simple ripple carry circuit is shown here for the slice  Actual implementation depend on the technology in which implemented.

19. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU19 Carry chain implementation  CMOS – Manchester carry chain using precharge pulldown logic works well.  ECL – Carry look-ahead circuitry works well as ECL allows for large fan-in wired OR gates.

20. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU20 Multibit implementation

21. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU21 Function codes for a multifunction ALU The G values for the various logic functions By setting the value of the G inputs, the output is the corresponding logic function of the data which comes in on the select inputs. Need the results block to route the P result.

22. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU22 Binary Subtraction  Much like addition but now choose P = A xnor B K = A B’  Diff D = A xor B xor Bin = A xnor B xnor Bin  Borrow Out Bout=P Bin + P’ K’

23. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU23 The codes to have the ALU work  Consider as we go to the sliced ALU  Logic function done in the P generic unit  Math uses all the blocks FunctionPKRCin A12---12--- A and B8--12--- OR14---12--- A + B + Cin 616Cin A+B6160 Incr A12361 A – B9490 or Bin

24. 1/8/2007 - L3 Data Path Design Copyright 2006 - Joanne DeGroat, ECE, OSU24 Multibit implementation