1. 1 Microprocessor-based systems Course 2 General structure of a computer

2. 2 Components of a computer system  Classic computer model (J. von Neumann) Control unit (CU) Arithmetical and logical unit (ALU) Memory (M) Input device(s) (ID) Output device(s) (OD) M CU DIDI DEDE ALU Data and program input Data output CPU=CU+ALU Central Processing Unit

3. 3 Components of a computer system  Microprocessor-based computer system – a bus-based system μPμP I/O Interface Memory

4. 4 The Central Processing Unit (CPU)  Control Unit (CU) Responsible for:  Instruction fetch (read)  Instruction decoding (interpretation)  Generation of command signals needed to execute the instruction It is a sequential circuit (state automatom)  The Arithmetical and Logical Unit (ALU) Executes arithmetical and logical operations:  Arithmetic: +,-,/,*, modulo, comparisons  Logic: SI, SAU, NU,  Shifts and rotations Usually it is a combinational circuit  Registers General purpose registers (GR)  Holds data  Take part in arithmetic and logic operations Special purpose registers ():  Addressing registers  Status register  Test registers  Control registers CPU CU PhG CGRI ID + CCBPC SR GR R1 Rn System Bus R2 … ALU

5. 5 Control Unit (CU)  The brain of the computer  It is composed of: Clock generator (CG)  Generates the clock (synchronization) signal Phase generator (PhG)  Generates the phases needed for instruction execution The Instruction Decoder (ID) and the Command and Control Block (CCB)  Interpret the instructions and generate command signals needed for instruction execution Instruction register IR  Keeps the current instruction Program counter PC  Keeps the address of the next instruction (to be executed) (Program) Status Register (SR) UC PhG CG IR ID + CCB PC SR Commands Address Instructions

6. 6 Arithmetical and Logical Unit  Ac – Accumulator register Keeps one of the operands and the result  R – register for the 2 nd operand  SR Status register R Ac ALU n n n n n Operation SR

7. 7 Arithmetical and Logical Unit  One bit adder with carry S i = A i + B i + T i-1 C i = A i *B i +C i-1 *(A i + B i ) Ti-1 Si CiCi Ai Bi

8. 8 n bits adder n-1 S n-1 B n-1 A n-1 C n-1 C n-2 11 S1S1 B1B1 A1A1 C1C1 C0C0 00 S0S0 B0B0 A0A0 C -1

9. 9 Adding operation with 2 registers 00 D0D0 11 D1D1 A1A1  n-1 D n-1 A n-1 A0A0 B0B0 B1B1 B n-1 CLKB Ad CLKA Step OperationCommands 1 Clear A Transfer D → B (operand 1) Ad = 0, CLKA = П (impuls) CLKB = П 2 Transfer B → A, D → B (operand 2) Ad = 1, CLKA = П, CLKB = П 3 A ← A + BAd = 1, CLKA = П

10. 10 Circuit for adding and subtraction in 2th complement  For adding: Ad/Sub = 0  For subtraction the second operand is complemented Ad/Sub=1 00 D0D0 11 D1D1 A1A1  n-1 D n-1 A n-1 A0A0 B0B0 B1B1 B n-1 CLKB CLKA Ad / Sub T0T0 T1T1 T n-1

11. 11 Logical unit with 4 operations MUX 4:1 C i-1 A i-1 Operation code B i-1 MUX 4:1 CiCi AiAi BiBi

12. 12 Multiply operation 1100 * 12 * 1010 10 0000 1100 0000 1100 1111000 = 78H = 120 Modified multiply operation: 00000000 Acumulator (AC) “0” → 0000000 0 Shift right “1” → 1100 Adding 0001100 0 Partial product 000110 00 Shift right “0” → 00011 000 Shift right “1” → 1100 Adding 1111 000 Final product

13. 13 Implementation of the multiply operation  (n+1) Command Device Shift right X Q0Q0 Q1Q1 Q n-1... B0B0 B1B1 B n-1... BSBS A0A0 A1A1 A n-1... ASAS Q S Y Clear Write Test Shift right Write

14. 14 Multiply algorithm 1. Write the operands into the registers B ← X, Q ← Y, clear the accumulator A ← 0 2. Complement the operands if they are negative 3. Test Q 0 Q 0 = 0, shift A and Q to the right Q 0 = 1, add A = B + A and shift A and Q to the right 4. Repeat step 3 until Y n-1 get into Q 0. In the last step the shift is not necessary 5. A S = B S + Q S 6. Complement the result if A S = 1

15. 15 Division circuit Sum, Diference Control device X Q0Q0 Q1Q1 Q n-1... B0B0 B1B1 B n-1... BSBS A0A0 A1A1 A n-1... ASAS Q S Y Ad / Sc

16. 16 Division algorithm 1.Load the first operand in registers A and Q Load the second operand in register B 2.Memorize A S + B S in Q S. If A S = 1, complement A, Q B S = 1, complement B 3.Tests: a.A ≥ B, overflow b.B = 0, division by 0 c.A = 0 and Q < B, result = 0 4.Shift A, Q to the left and put 0 in Q 0 5.Subtract B from A and put the result in A. If A S = 0, shift left A, Q and put 1 in Q 0 A S = 1, add B to A, shift left A, Q and put 0 în Q 0 6. Repeat step 5 for n times 7. Round the result: if A ≥ B, add 1 to Q 8. If Q S = 1 complement register Q

17. 17 Adding in floating point representation 1.Load the operands into registers 2.Compare the exponents (5 cases): e x = e y, add mantissas and copy the exponent e x > e y and (e x – e y ) < mantissa’s bits, than m y is aligned by shifting to the rights with e x -e y positions and than add m x with m y e x >> e y and (e x – e y ) ≥ mantissa’s bits, than copy X into the result e x < e y şi (e y – e x ) < mantissa’s bits, than mantisa m x is aligned by shifting to the rights with e y -e x positions and than add m x with m y e x << e y şi (e y – e x ) ≥ mantissa’s bits, than copy Y into the result 3. Normalize the result. Test the bits around the decimal point and if necessary shift the mantissa to the right or to the left and increment or decrement the exponent

18. 18 Adder circuit for floating point numbers Σ X expmantissaS Y A expmantissaS B Shift Load Shift Load Control device Exp A Exp B Increment

19. 19 Multiply and division in floating point representation  Multiply is made as follows: add the exponents multiply the mantissas normalize the result  Division is made as follows: subtract exponents divide mantissas normalize the result Σ / Δ exp mantissa A A mantissa B Inc/Dec A Shift Left/right A Ad/ Sc S exp B Inc/Dec B S Comand device Shift left/right B

20. 20 Design of a simple computer Design steps: 1. Establish the destination and the domain of use for the computer; 2 Define the instruction set and instruction format; 3 Design the block scheme of the central processing unit; 4 Decompose instructions into micro-operations and phases; 5 Define the logical equations/functions for the micro- commands; 6 Design the logical scheme for the PhG and CCB; 7 design the other modules: IR, PC, GR, ALU, SR, CG; 8 Design of memory modules; 9 Design of I/O interfaces; 10 Optimize the scheme through steps 2-9

21. 21 Simple computer: Design steps  Destination: General purpose computer Special destination computers:  embedded computers  signal processing computers  control systems High performance computers:  Parallel and distributed systems (GRID, Cloud, etc.)  Instruction set: Instruction format: (length and fields)  Fixed:  Variable Operation Types:  Arithmetic  Logic  Transfer  Jump and branch  Stack operations, etc.