1. Soft errors in adder circuits Rajaraman Ramanarayanan, Mary Jane Irwin, Vijaykrishnan Narayanan, Yuan Xie Penn State University Kerry Bernstein IBM

2. Ramanarayanan 177/MAPLD ‘04 Talk Overview Introduction Soft errors  Introduction  Impact on data-path circuits  Modeling soft errors in logic circuits Experimental setup and methodology  Error injection mechanism  Adder circuits considered  Methodology Results Conclusions and Future work (Lessons learned)

3. Ramanarayanan 177/MAPLD ‘04 Talk Overview

4. Ramanarayanan 177/MAPLD ‘04 Introduction Soft errors, which are transient errors caused due to external radiations, affected mainly memory circuits. Soft error rates (SER) in data-path structures and combinational logic have been increasing due to:  Continuous device scaling.  Voltage scaling and increased speed.  increasing pipeline lengths.

5. Ramanarayanan 177/MAPLD ‘04 Introduction Adder circuits form an integral part of data-path. Hence, in this work, we  Analyze SER in different types of adder circuits.  Analyze the effect of voltage and frequency scaling on SER.  Experimented techniques to improve the error rates in adder circuits based on above results.

6. Ramanarayanan 177/MAPLD ‘04 Talk Overview

7. Ramanarayanan 177/MAPLD ‘04 Soft errors - Introduction Soft errors or transient errors are circuit errors caused due to excess charge carriers induced primarily by external radiations. These errors cause an upset event but the circuit it self is not damaged.

8. Ramanarayanan 177/MAPLD ‘04 Soft errors - Sources At ground level, there are three major contributors to Soft errors.  Alpha particles emitted by decaying radioactive impurities in packaging and interconnect materials.  Cosmic Ray induced neutrons cause errors due the charge induced due to Silicon Recoil.  Neutron induced 10 B fission which releases a Alpha particle and 7 Li.

9. Ramanarayanan 177/MAPLD ‘04 B S D p substrate G n+ n channel Soft Errors - The Phenomena + - A particle strike Current

10. Ramanarayanan 177/MAPLD ‘04 Soft Errors - The Phenomena V DD V out CLCL V in A particle strike Bit Flip !!!

11. Ramanarayanan 177/MAPLD ‘04 Soft errors - Impact on data-path circuits In data-path circuits, an error is caused when the pulse generated by a particle is latched on at the output by a flip-flop. Here, the critical charge (Q critical ), can be defined, as the minimum charge required to latch on to the pulse. There are three masking effects in combinational circuits that affect the propagation of any given pulse:  Logical masking  Electrical masking  Latching window masking

12. Ramanarayanan 177/MAPLD ‘04 REGISTERSREGISTERS I1 I2 I3 I4 I5 I6 I7 C E D B REGISTERSREGISTERS O2 O1 1 1 1 0 1 0 1 0 Soft error No Soft error Particle strike Effect of electrical masking Masking effects in data-path

13. Ramanarayanan 177/MAPLD ‘04 Modeling soft errors *Courtesy - K. Bernstein * Simulated 150 MEV Proton-induced charge collection for 90 nm and 130 nm bulk technologies; per-bit SER per unit collection

14. Ramanarayanan 177/MAPLD ‘04 Modeling soft error in logic circuits Massengill et al. developed a model for a tool, which would predict the probability of an error occurring in a given combinational circuit. Probability that a random particle hit (resulting in a current pulse) at a node N in a clock cycle C will be latched on by the output latch or flip-flop (P SF C,N ). Probability of soft errors occurring in a given circuit can be determined using the above probability.

15. Ramanarayanan 177/MAPLD ‘04 Modeling soft error in logic circuits In this work, we propose a model that can accurately models the above probability. We borrow the term “Timing Vulnerability” defined in the work by S. Mukherjee et al.  This is defined as the fraction of time in a clock cycle in which a given node in a circuit is vulnerable (t v ).  For example, a latch has a t v of 50%. Thus, P SF C,N = ∑ P Qcoll * t v, where P Qcoll is the collected charge at a given node.

16. Ramanarayanan 177/MAPLD ‘04 Talk Overview

17. Ramanarayanan 177/MAPLD ‘04 Error injection mechanism Based on the models provided by previous works,  We modeled our current pulse as an exponential wave form with a pulse width of 50 ps in our HSPICE simulations. Charge colleted at a node can be determined using the following expression:  Q = ∫ I d dt, where I d =Drain Current.

18. Ramanarayanan 177/MAPLD ‘04 Adder Designs Considered € € € € P0,G0P1,G1P2,G2P3,G3 S0S1S2S3 € € € P0,G0P1,G1P2,G2P3,G3 S0S1S2S3 € € (a) Brent-kung (B-K)(b) Kogge-stone (K-S) C0 C1C2C3 P3P2P1P0 C0 C1C2C3 P3P2P1P0

19. Ramanarayanan 177/MAPLD ‘04 Methodology Our analysis consists of:  Measuring Q critical at different nodes affecting different outputs in B-K adders.  Comparing B-K with K-S and Ripple Carry (RC) adders.  Measuring Q critical and t v after scaling voltage and frequency. Next we consider techniques to improve the above two quantities to increase the robustness of adders:  Use a Flip-Flop with better t v values. Using a Semi-dynamic Flip-Flop (SDFF) instead of a Transmission gate Flip-Flop (TGFF) used initially.  Increase threshold voltage, which increases Q critical. All circuits were custom designed and laid out in 70nm technology.

20. Ramanarayanan 177/MAPLD ‘04 Talk Overview

21. Ramanarayanan 177/MAPLD ‘04 Q critical for B-K, K-S and RC adders

22. Ramanarayanan 177/MAPLD ‘04 Results – B-K adders For B-K adders (at node C0):  Q critical ’s for a node to cause a flip at all the sum outputs are similar.  Q critical for all outputs flipping together is higher.

23. Ramanarayanan 177/MAPLD ‘04 Adder comparisons For B-K and K-S, Q critical at a node for flipping different outputs are comparable while RC has progressively increasing Q critical. Q critical is smaller in K-S adders due to shortest path carry chains. Also KS adders have greater area susceptible to soft errors due to larger number of carry cells. B-K adder has more nodes that fan’s out equally to many outputs  Hence, a single particle strike at a node can cause multi-bit errors.

24. Ramanarayanan 177/MAPLD ‘04 Voltage and frequency scaling

25. Ramanarayanan 177/MAPLD ‘04 Voltage and Frequency scaling The adders were run at 1 GHz, 0.833GHz and 0.5 GHz with 1V, 0.8 V and 0.6V as supply voltages respectively. As both voltage and frequency are scaled, Q critical reduces slightly at many nodes. Reducing frequency reduces t v, but reduction in Q critical plays a much important role.

26. Ramanarayanan 177/MAPLD ‘04 Optimization Techniques Using Flip-Flop with lesser set-up and hold time (SDFF)  Improves timing vulnerability.  Also improves Q critical for multi-bit errors. Increasing threshold voltage  Increases Q critical as it increases the gain of the logic circuit.  But it increases the timing vulnerability also.

27. Ramanarayanan 177/MAPLD ‘04 Conclusions and lessons learnt The timing vulnerability determines the occurrences of multi-bit errors in adders. Trade-offs have to be considered in using different type of adders.  K-S adders have lesser Q critical and higher soft error rate.  Multi-bit errors can be more common in B-K adders Voltage and frequency scaling worsens the soft error rate. Techniques to improve Q critical and t v were presented.  Trade-offs in choosing these techniques.

28. Ramanarayanan 177/MAPLD ‘04 References L. W. Massengill, A. E. Baranski, D. O. V. Nort, J. Meng, and B. L. Bhuva. Analysis of Single-Event Effects in Combinational Logic – Simulation of the AM2901 Bitslice Processor. IEEE Trans. on Nuclear Science, 47(6):2609–2615, December 2000. S. K. Reinhardt and S. Mukherjee. Transient Fault Detection via Simultaneous Multithreading. International Symposium on Computer Architecture, pages 25–36, July 2000.