1. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures. n Switch logic. n Non-standard gate structures.

2. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Combinational logic expressions n Combinational logic: function value is a combination of function arguments. n A logic gate implements a particular logic function. n Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

3. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Gate design Why designing gates for logic functions is non-trivial: –may not have logic gates in the libray for all logic expressions; –a logic expression may map into gates that consume a lot of area, delay, or power.

4. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Boolean algebra terminology n Function: f = a’b + ab’ n a is a variable; a and a’ are literals. n ab’ is a term. n A function is irredundant if no literal can be removed without changing its truth value.

5. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Completeness n A set of functions f1, f2,... is complete iff every Boolean function can be generated by a combination of the functions. n NAND is a complete set; NOR is a complete set; {AND, OR} is not complete. n Transmission gates are not complete. n If your set of logic gates is not complete, you can’t design arbitrary logic.

6. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Static complementary gates n Complementary: have complementary pullup (p-type) and pulldown (n-type) networks. n Static: do not rely on stored charge. n Simple, effective, reliable; hence ubiquitous.

7. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Static complementary gate structure Pullup and pulldown networks: pullup network pulldown network V DD V SS out inputs

8. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Inverter a out +

9. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR NAND gate + b a out

10. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR NOR gate + b a out

11. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR AOI/OAI gates n AOI = and/or/invert; OAI = or/and/invert. n Implement larger functions. n Pullup and pulldown networks are compact: smaller area, higher speed than NAND/NOR network equivalents. n AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.

12. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR AOI example out = [ab+c]’: symbolcircuit and or invert

13. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Pullup/pulldown network design n Pullup and pulldown networks are duals. n To design one gate, first design one network, then compute dual to get other network. n Example: design network which pulls down when output should be 0, then find dual to get pullup network.

14. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Dual network construction dummy a bc a b c

15. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Switch logic n Can implement Boolean formulas as networks of switches. n Can build switches from MOS transistors— transmission gates. n Transmission gates do not amplify but have smaller layouts.

16. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Switch logic network a b 0 1 about 00X 011 100 11X

17. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Another switch logic network a b r s about 00X 01r 10s 11X

18. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Switch-based mux

19. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Types of switches

20. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Behavior of n-type switch n-type switch has source-drain voltage drop when conducting: –conducts logic 0 perfectly; –introduces threshold drop into logic 1. V DD V DD - V t

21. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR n-type switch driving static logic Switch underdrives static gate, but gate restores logic levels. V DD V DD - V t

22. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR n-type switch driving switch logic Voltage drop causes next stage to be turned on weakly. V DD V DD - V t V DD

23. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Behavior of complementary switch n Complementary switch products full-supply voltages for both logic 0 and logic 1: –n-type transistor conducts logic 0; –p-type transistor conducts logic 1.

24. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Charge sharing n Values are stored at parasitic capacitances on wires:

25. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Charge sharing example 1 1 0 00 11

26. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR DCSL gate

27. FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR MTCMOS gate