1. Complementary CMOS Logic Style Construction (cont.)
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

2. Example Gate: NAND Digital Integrated Circuits © Prentice Hall 1995
Introduction

3. Example Gate: NOR Digital Integrated Circuits © Prentice Hall 1995
Introduction

4. Example Gate: COMPLEX CMOS GATE
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

5. 4-input NAND Gate Vdd Out GND In1 In2 In3 In4
Digital Integrated Circuits
© Prentice Hall 1995
Introduction
Vdd
Out
GND
In1
In2
In3
In4

6. Nand / Nor Gates

7. Standard Cell Layout Methodology
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

8. Two Versions of (a+b).c Digital Integrated Circuits
© Prentice Hall 1995
Introduction

9. Properties of Complementary CMOS Gates
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

10. Complex Gate Structures
Vdd
And-Or-Invert (AOI) C B A B C A
Out
Out = A+(B*C) ... B A C
How to add terms?
Gnd

11. Demorgan’s Law in Action
OAI/AOI Duality A C B
Vdd
Gnd
Out
Or-And-Invert (OAI) A B C
Demorgan’s Law in Action
Switch from:
Out = A+(B*C) ...
To:
Out = A*(B+C) ...

12. Demorgan’s Law in ActionB
Vdd
Gnd
Out
Or-And-Invert (OAI) A B C
Out = A*(B+C) ...

13. Demorgan’s Law in ActionB
Vdd
Gnd
Out
Or-And-Invert (OAI) A B C
Out = A*(B+C) ...

14. Demorgan’s Law in ActionB
Vdd
Gnd
Out
Or-And-Invert (OAI) A B C
Out = A*(B+C) ...

15. Demorgan’s Law in ActionB
Vdd
Gnd
Out
Or-And-Invert (OAI) A B C
Out = A*(B+C) ...

16. Demorgan’s Law in Action
Vdd
Or-And-Invert (OAI) C A B A C B
Out
Out = A*(B+C) ... A C B
What is the Magic command to do this?
Gnd

17. Complex (AOI/OAI) Gates

18. Quiz

19. Step by Step Layout of XNOR Gate
The equation for XNOR is:
f = (a * b) + (a' * b')
using DeMorgan's law on each of the two terms gives:
f = (a'+ b')' + (a + b)'
using DeMorgan's law on the two terms together gives:
f = ((a'+ b') * (a + b))'
This could be directly implemented with a single complementary CMOS gate: the equation is in a simple negated product of sums form. This form can be implemented with the standard Or-And-Invert (OAI) style gate.

20. Non-Inverted Inputs
However, using DeMorgan's law one more time on the left term gives:
f = ((a * b)' * (a + b))’
This form uses no inverted inputs and can be implemented with two gates a NAND gate and an OAI gate. a b f

21. Now lets lay it out Start with Vdd! and GND! power buses.
Without any more information, about the use of this cell, make the power and ground lines in metal 1
sized 3 and 3 apart.
Use poly as inputs A B and guess that C might be used.

23. Step by Step
Now put in a stripe of N diffusion (green) creating a series of 2 n-channel transistors for the pull down structure for the first NAND gate.
Also put in a stripe of P diffusion (brown) and center connection to Vdd to plan for a parallel connection for the pull up structure for the NAND gate.

25. By step Now finish wiring up the NAND gate.
Strap the two ends of the pull-up parallel transistors and tie them to the series pull down.
Use the polly line, C to tie them together.

27. Or Gate
Begin to add the OR structure for the OAI gate above the NAND gate transistors.
This allows us to share the poly lines for A and B inputs.
Since we are building an OR structure, its series in the pull up and parallel in the pull down.

29. Oh, Oh!
No good way to get power up to the end of that pull-up structure, shown above.
So, we have to swap the pull-ups for the NAND gate and the OR gate
Note that we are only half done with the swap in this picture, the output is not wired correctly.

31. We have done several steps
We fixed the output of the NAND so that it uses the correct pull-up structure.
We added a new pull-up transistor in parallel with the two series transistors of the OR structure on the OAI.
It's in parallel because it provides a second path to Vdd for the output.
Note the "L" of metal indicating where the output will come from.
We added a complementary series pull-down transistor for the OAI as well.

33. Finish up
Here, all we did was add the output strap between the pull-up and pull down structures, completing the OAI gate.
We are still missing the WELL contact cuts.
I did not finish, 'cause I was late for class.

35. Question: Is this the same circuit? Does it compute the same function?
Trace it out and see!

37. Lab 2: Full Adder Sum = A xor B xor C Cout = AB + AC + BC expand sum
Sum = ABC+AB’C’+A’BC’+A’B’C
(exactly 1 or 3 inputs true)
use Cout to help generate Sum
Sum = ABC + Cout’(A+B+Cin)

38. Full Adder (4 gates)

39. Full Adder (4 gates)

40. One Solution (125x136)

42. Lab 3: 8 Bit Ripple Carry Adder

43. X-panded