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Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 3, 2014 Gates from Transistors.

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Presentation on theme: "Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 3, 2014 Gates from Transistors."— Presentation transcript:

1 Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 3, 2014 Gates from Transistors

2 Previously Simplified models for reasoning about transistor circuits –Zeroth-order Penn ESE370 Fall2014 -- DeHon 2

3 Today How to construct static CMOS gates Penn ESE370 Fall2014 -- DeHon 3

4 Outline Circuit understanding (preclass) –Gate function identification Static CMOS –Structure –Inverter –Construct gate –Inverting –Cascading Penn ESE370 Fall2014 -- DeHon 4

5 Why Zeroth Order Useful? Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Make sure understand logical function (achieve logical function) before worrying about performance details Penn ESE370 Fall2014 -- DeHon 5

6 What gate? Penn ESE370 Fall2014 -- DeHon 6

7 What function? Penn ESE370 Fall2014 -- DeHon 7

8 DeMorgan’s Law /f = a + b What is f? Penn ESE370 Fall2014 -- DeHon 8

9 What function? Penn ESE370 Fall2014 -- DeHon 9

10 Static CMOS Gate Penn ESE370 Fall2014 -- DeHon 10

11 Static CMOS Gate Structure Penn ESE370 Fall2014 -- DeHon 11

12 Static CMOS Gate Structure Penn ESE370 Fall2014 -- DeHon 12

13 Static CMOS Gate Structure Drives rail-to-rail –Power rails are Vdd and Gnd –output is Vdd or Gnd Inputs connects to gates  load is capacitive Once charge capacitive output, doesn’t use energy –(first order) Output actively driven Penn ESE370 Fall2014 -- DeHon 13

14 Inverter Out = /in Penn ESE370 Fall2014 -- DeHon 14

15 Inverter Penn ESE370 Fall2014 -- DeHon 15

16 Why zeroth-order adequate? Static analysis – can ignore capacitors Capacitive loads – resistances don’t matter Feed forward for gates – –don’t generally have loops –can work forward from known values Logic drive to ground or Vdd (rail-to-rail) –Don’t have to reason about intermediate voltage levels Penn ESE370 Fall2014 -- DeHon 16

17 What zeroth-order not tell us? Delay Dynamics Behavior if not –Capacitively loaded –Acyclic (if there are Loops) –Rail-to-rail drive (voltages between 0 and Vdd) Penn ESE370 Fall2014 -- DeHon 17

18 Gate Design Example Penn ESE370 Fall2014 -- DeHon 18

19 Gate Design Design gate to perform: f=(/a+/b)*/c Penn ESE370 Fall2014 -- DeHon 19

20 f=(/a+/b)*/c Strategy: 1.Use static CMOS structure 2.Design PMOS pullup for f 3.Use DeMorgan’s Law to determine /f 4.Design NMOS pulldown for /f Penn ESE370 Fall2014 -- DeHon 20

21 f=(/a+/b)*/c PMOS Pullup for f? Penn ESE370 Fall2014 -- DeHon 21

22 f=(/a+/b)*/c Use DeMorgan’s Law to determine /f. What is /f ? Penn ESE370 Fall2014 -- DeHon 22

23 f=(/a+/b)*/c NMOS Pulldown for /f? Penn ESE370 Fall2014 -- DeHon 23

24 f=(/a+/b)*/c Penn ESE370 Fall2014 -- DeHon 24 a c b

25 Static CMOS Source/Drains With PMOS on top, NMOS on bottom –PMOS source always at top (near Vdd) –NMOS source always at bottom (near Gnd) Penn ESE370 Fall2014 -- DeHon 25

26 TA Office Hours M, W Poll for times Monday 5-9pm Poll for times Wednesday 5-9pm Penn ESE370 Fall2014 -- DeHon 26

27 Inverting Gate Penn ESE370 Fall2014 -- DeHon 27

28 Inverting Stage Each stage of Static CMOS gate is inverting Penn ESE370 Fall2014 -- DeHon 28

29 How do we buffer? Penn ESE370 Fall2014 -- DeHon 29

30 How implement OR? Penn ESE370 Fall2014 -- DeHon 30

31 Cascading Stages Penn ESE370 Fall2014 -- DeHon 31

32 Stages Can always cascade “stages” to build more complex gates Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality –but may not be smallest/fastest/least power Penn ESE370 Fall2014 -- DeHon 32

33 Implement: f=a*/b Pullup? Pulldown? Penn ESE370 Fall2014 -- DeHon 33

34 f=a*/b Penn ESE370 Fall2014 -- DeHon 34

35 Course Alum – IBM Jobs Brian Yavoich – VLSI SRAM circuit design at IBM –Took this course Fall 2011 –Advertising full-time and summer hardware jobs at IBM Penn ESE370 Fall2014 -- DeHon 35

36 Big Idea Systematic construction of any gate from transistors 1.Use static CMOS structure 2.Design PMOS pullup for f 3.Use DeMorgan’s Law to determine /f 4.Design NMOS pulldown for /f Penn ESE370 Fall2014 -- DeHon 36

37 Admin Office hours –Ron (TA): Monday and Wednesday, Ketterer –Tuesday: Andre 4:15-5:30pm Levine 270 Thursday: HW1 due identify gates; use electric Friday in Detkin (RCA) Lab –Please read through HW2, Lab1 details –Bring USB drive with you to lab on Friday to store waveforms Penn ESE370 Fall2014 -- DeHon 37

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