1. Chapter 2Basic Digital Logic1 Chapter 2

2. Basic Digital Logic2 Outlines  Basic Digital Logic Gates  Two types of digital logic circuits Combinational logic circuits Sequential logic circuits  Combinational logic circuit design Using sum of product Using product of sum  Karnaugh map: Minimization of logic circuits Without don’t care term With don’t care term  Construction from smaller components  Sequential logic circuit

3. Chapter 2Basic Digital Logic3 Switches  Abstraction of building block of digital computers  Basic logic functions AND OR NOT B A A A B

4. Chapter 2Basic Digital Logic4 Basic Digital Logic Gates NOT gate AND gate OR gate XOR gate NAND gate NOR gate XNOR gate

5. Chapter 2Basic Digital Logic5 Two types of digital logic circuits  Combinational logic circuits Output depends only on its input at that time.  Sequential logic circuits Output depends both on  its previous output and  its input at that time Combinational Logic Circuit Sequential Logic Circuit

6. Chapter 2Basic Digital Logic6 Combinational Logic Circuit

7. Chapter 2Basic Digital Logic7 How to design a combinational logic circuit  Decide how to encode input and output in 0 and 1  Describe each bit of the output in term of input Truth table Logical function  Construct a logic circuit from the logical function

8. Chapter 2Basic Digital Logic8 Truth table and logical function out = f (in 1, in 2, …) in 1 in 2 …out 0001 0010 010… ………… 1110

9. Chapter 2Basic Digital Logic9 Boolean Logic  Basic Boolean operations AND: X  Y, X & Y, X Y, X  Y OR: X  Y, X + Y NOT: ~X, X’, X  Any Boolean expressions can be described in: Disjunctive normal form (DNF) /sum of product Conjunctive normal form (CNF) / product of sum

10. Chapter 2Basic Digital Logic10 Example: Exclusive OR (XOR)  output =  X Y + X  Y XYoutput 000 011 101 110

11. Chapter 2Basic Digital Logic11 Construct Sum of Products  Find out all conditions when the function is true X  Y = T(1) when  X=0, Y=1 =>  X Y =1  X=1, Y=0 => X  Y = 1 OR the conditions   X Y + X  Y Sum of products XYoutput 000 011 101 110 minterm

12. Chapter 2Basic Digital Logic12 Exclusive OR (XOR): Sum of products  output =  X Y + X  Y minternXYoutput XYXY 000  X Y 011 X  Y 101 X Y110 X Y output

13. Chapter 2Basic Digital Logic13 Construct Product of Sums  Find out all conditions when the negation of the function is true X  Y = F(0) when  X=0, Y=0 => X + Y = 0  X=1, Y=1 =>X +Y = 0 AND the conditions  ( X + Y )(X +Y) Product of sum XYoutput 000 011 101 110 maxterm

14. Chapter 2Basic Digital Logic14 Exclusive OR (XOR)  output = ( X + Y )(  X +  Y ) X Y output maxtermXYoutput X + Y000 X +  Y 011 101  X +  Y 110

15. Chapter 2Basic Digital Logic15 Karnaugh Map (K-map)

16. Chapter 2Basic Digital Logic16 2-variable K-map A B 01 0 1 ABX 00 01 10 11

17. Chapter 2Basic Digital Logic17 3-variable K-map ABCX 000 001 010 011 100 101 110 111 AB C 00011110 0 1

18. Chapter 2Basic Digital Logic18 4-variable K-map ABCDX 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AB CD 00011110 00 01 11 10

19. Chapter 2Basic Digital Logic19 Full Adder Full adder A B Ci S Co ABCiSCo 00000 00110 01010 01101 10010 10101 11001 11111

20. Chapter 2Basic Digital Logic20 Full Adder ABCSCo 00000 00110 01010 01101 10010 10101 11001 11111 AB C 00011110 00101 11010 AB C 00011110 00010 10111 S=A’B’C+A’BC’+ABC+AB’C’ Co=AB+BC+AC

21. Chapter 2Basic Digital Logic21 Encoder A3 A2 A1 X1 A0 X0 A3A2A1A0X1X0 0000XX 000100 001001 0011XX 010010 …XX 100011 …XX 1111XX

22. Chapter 2Basic Digital Logic22 Encoder A3A3 A2A2 A1A1 A0A0 X1X1 X0X0 0000XX 000100 001001 0011XX 010010 …XX 100011 …XX 1111XX A 3 A 2 A 1 A 0 00011110 00X1X1 010XXX 11XXXX 100XXX X 1 =  A 1  A 0

23. Chapter 2Basic Digital Logic23 Encoder A3A3 A2A2 A1A1 A0A0 X1X1 X0X0 0000XX 000100 001001 0011XX 010010 …XX 100011 …XX 1111XX A 3 A 2 A 1 A 0 00011110 00X0X1 010XXX 11XXXX 101XXX X 0 = A 1 +A 3

24. Chapter 2Basic Digital Logic24 Decoder 2 - 4 decoder b3b2b1b0b3b2b1b0 a1a0a1a0 If a 1 a 0 is a binary i, b i is 1 and b j is 0 when j  i. a1a1 a0a0 b3b3 b2b2 b1b1 b0b0 000001 010010 100100 111000

25. Chapter 2Basic Digital Logic25 Decoder a1a1 a0a0 b3b3 b2b2 b1b1 b0b0 000001 010010 100100 111000 b 3 = a 1 a 0 b 2 = a 1  a 0 b 1 =  a 1 a 0 b 0 =  a 1  a 0 b3b3 b2b2 b0b0 b1b1 a0a0 a1a1

26. Chapter 2Basic Digital Logic26 Multiplexor 2-1 multiplexor D1D0D1D0 x S X = D s SD1D1 D0D0 x 0000 0011 0100 0111 1000 1010 1101 1111

27. Chapter 2Basic Digital Logic27 Multiplexor SD1D1 D0D0 x 0000 0011 0100 0111 1000 1010 1101 1111 D 1 D 0 S 00011110 0 0110 1 0011 X =  S D 0 + S D 1

28. Chapter 2Basic Digital Logic28 Multiplexor X =  S D 0 + S D 1 D 1 D 0 S X

29. Chapter 2Basic Digital Logic29 Construction from Smaller Components

30. Chapter 2Basic Digital Logic30 2-bit Full Adder 1 1 A 1 A 0 0 1 + B 1 B 0 + 1 0 0 C S 1 S 0 FA 0 FA 1 A 1 B 1 A 0 B 0 Ci=0 C S 1 S 0 A B Ci Co S A B Ci Co S 2-bit full adder

31. Chapter 2Basic Digital Logic31 4-bit Full Adder 1 0 1 1 0 1 1 1 + 1 0 0 1 0 A 1 A 0 B 1 B 0 + C S 1 S 0 2FA 0 2FA 1 A 1 B 1 A 0 B 0 Ci=0 C S 1 S 0 A B Ci Co S A B Ci Co S 2 22 2 2 2 4-bit full adder

32. Chapter 2Basic Digital Logic32 Sequential Circuit

33. Chapter 2Basic Digital Logic33 Clock Signal oscillating between 0 and 1 clock cycle time / clock period Rising edge Falling edge Edge-triggered clocking The state of the sequential circuits changes on the clock edge.

34. Chapter 2Basic Digital Logic34 Types of sequential circuits  Synchronous circuits With clock Use in digital computers  Asynchronous circuits Without clock

35. Chapter 2Basic Digital Logic35 SR Latch R Q’ S Q 0 1 1 0 0 1 set R Q’ S Q 1 0 0 1 1 0 reset R Q’ S Q 0 0 1/0 0/1 1/0 hold R Q’ S Q 1 1 ? ? ? ? unstable

36. Chapter 2Basic Digital Logic36 D Latch C D Q QQ 0 0 Q0Q0 0 0 Q0Q0 Q0Q0 C D Q QQ 0 1 Q0Q0 0 0 Q0Q0 Q0Q0 C D Q QQ 1 0 0 0 1 0 C D Q QQ 1 1 1 1 0 0 Q0Q0 0 CDQCDQ C=0 hold data C=1 load data

37. Chapter 2Basic Digital Logic37 D Flip-flop D latch DCDC DCDC QQ DCDC Q  Q 1010 xDxD QDQD D latch DCDC DCDC QQ DCDC Q  Q 0101 xxxxQQQQ D latch DCDC DCDC QQ DCDC Q  Q 0000 xxxxxxxx D latch DCDC DCDC QQ DCDC Q  Q 1111 xDxDDDDD CDQCDQ C=1  0 load data

38. Chapter 2Basic Digital Logic38 Registers D flip-flop clk D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 8-bit REGISTER D in D out clk 8 8 CDQCDQ Set-up time Hold time

39. Chapter 2Basic Digital Logic39 Register Files n-2 n decoder Register n-1 Register n-2 Register 0... n n-1 n-2 0 Write Register number Data in 8 n-1 MUX Data out 8

40. Chapter 2Basic Digital Logic40 Finite State Machines Next-state function (Combinational) Current State (registers) Output function (Combinational) Inputs Outputs

41. Chapter 2Basic Digital Logic41 Counter 0 -> 3 clk abab Current StateNext State abAB 0001 0110 1011 1100 A = a  b B =  b D Q  Q D Q  Q clk a b

42. Chapter 2Basic Digital Logic42 Counter with reset R clk abab reset R Current State Next State abAB 00001 00110 01011 01100 10000 10100 11000 11100 A =  R (a  b) B =  R  b D Q  Q D Q  Q R clk a b