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Laurent VUILLEMIN Platform Compile Software Manager Emulation Division The Veloce Emulator and its Use for Verification and System Integration of Complex.

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Presentation on theme: "Laurent VUILLEMIN Platform Compile Software Manager Emulation Division The Veloce Emulator and its Use for Verification and System Integration of Complex."— Presentation transcript:

1 Laurent VUILLEMIN Platform Compile Software Manager Emulation Division The Veloce Emulator and its Use for Verification and System Integration of Complex Multi-node SOC Computing System

2 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce 2

3 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce 3

4 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Verification Challenges 4 Systems Debug Software

5 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Hardware Development Typical Development Cycle System Verification Block-level Verification Design Cycle System Integration Software Development Fab Chip-level Verification Time to Market Hardware Development 5

6 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Hardware Development Typical System Development System Verification Block-level Verification Design Cycle System Integration Software Development Fab Chip-level Verification Time to Market 6

7 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Software Simulation Model is represented in Data Structures Compute and propagate signal values 7 module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout; always @ (posedge ck) begin if ( en ==1 ) dout = dout+step; end endmodule RTL Model module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout; always @ (posedge ck) begin if ( en ==1 ) dout = dout+step; end endmodule Test bench

8 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Clock Speed Scaling Stalls Emulation Required to Extend Performance Source: Recording Microprocessor History 4/6/2012 Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz http://queue.acm.org/detail.cfm?id=2181798

9 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Emulation 9 Multiples FPGA reproduce Model behavior from high level description Map RTL model in Programmable Logic module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout; always @ (posedge ck) begin if ( en ==1 ) dout = dout+step; end endmodule RTL Model Programmable Logic Control execution and get results

10 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Start Early – Continue for Entire SoC Life Architecture Phase Block-level Verification Fullchip/SoC Verification Software, Firmware & Device Drivers Systems Validation Post Silicon Bringup and Validation

11 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce 11

12 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Modern SOC environment CPU Arbiter Fabric UART Slave IF GPIO Slave IF PCI Express PHY Fabric Software Memory Software Memory Master IF Display Processor Display Processor PHY Slave IF SATA PHY Slave IF Ethernet PHY Slave IF USB PHY SlaveIF Master IF CPU Master IF SoC Embedded SW Debugger RSP JTAG 12

13 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com ICE use Model The emulator is connected to actual Hardware Veloce 13 External Hardware DUT Cables

14 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Ethernet Verification With ICE iSolve Ethernet Ethernet Network Live Traffic Stimulus Generation / Analysis Tools 14

15 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com 15 Co Emulation Testbench Xpress (TBX) Transactions High-speed Interface Testbench divided in 2 parts one in emulator the other in Station Communication via transactor Software sends commands that are interpreted by transactor to generate DUT stimulus PCI E 1/2 X-actor AGP 1/2 X-actor USB 1/2 X-actor 1/2 X- actor Testbench DUT Software Hardware

16 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Veloce Use Models USB PCIe Physical I/O Accelerated Transactors OVM/UVM SystemVerilog C/SystemC Simulation Acceleration Testbench Xpress.... iSolve Solutions VirtuaLAB Solutions USB Virtual Protocol Solutions SATA Video Ethernet Software Debug Codelink SW Debug VProbe Fast ISS QEMU Video SATA Co-Model Channels Physical Protocol Solutions Ethernet PCIe 16

17 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce 17

18 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Veloce 2 Architecture 18 Crystal2 Chip Maximus2 X 16 AVB2 X 64 + 40 SXB (Switch boards) + 4 CXB (clock board) Quattro2 + 6 SXB (Switch boards) 16 AVB2 + 1 CXB (clock board)

19 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Crystal 2 IC 19 Programmable Logic Array Control Memories Debug Resources Virtual Wire Logic Programmable Logic Array Set of LUT an Sequential elements Interconnect Network Memories : User Memories model Virtual Wire Logic Transport signals between chips Debug Resources Trace every Sequential element and memories Triggers Control Load configuration Control emulation

20 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software —Compile Software —Runtime Software Practical : Use Veloce to verify Veloce 20

21 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Software Overview 21 Emulator host NetworkNetwork Compile SW Configuration bitstream Runtime SW User design Compile Servers PC Farm Low Level SW Transform design in bistream User Interface Control Emulator Collect debug data

22 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Compile software 22 TBX RTLC Platform Compile Design +Testbench Design +Testbench Bitstream Gate netlist RTL Partition Testbench between SW and Emulator Perform RTL Synthesis Partitioning in Crystal Sytem Routing Crystal Place and Route Ressource Allocation

23 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Runtime Software Veloce DAC 2014 23 Emulator Message Bus Emulator Host Server LLSW Ressour ce Server Mainten ance Server Runtime Server User Message Bus UI Visibility Server

24 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce —Challenges —The verification infrastructure —Verifying ASIC —Verifying the Compilation software —Low level software integration —Firmware validation debug —Runtime software integration 24

25 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Challenges Complex system —ASIC —FPGAs Firmware —Mutliple software components Verifying all component of the system and their interactions Time to get a bug Size : —Detailed model of a full Emulator of next generatio will not fit in current generation 25

26 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Addressing the challenges Use a comodel approach for more abstraction level and connection with the software Divide verification in steps based on functionality Simplify the model by using different abstraction level depending on what functionality is tested Veloce DAC 2014 26

27 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Verification Infrastructure Veloce 27 More details on Veloce Crystal Control Crystal Control Control Chip LLSW on host Control Commands Veloce Control Bus

28 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Verification Infrastructure Veloce 28 Emulation model Emulator Crystal Control Crystal Control Software Control Chip Veloce Control Bus Transactor Nature of the Software, Transactor and Model in emulator depend on abstraction level

29 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com ASIC verification : example of Trace Veloce 29 Data SW translator Veloce Comands Comodel SW Emulation Model Crystal Control Macro Block Design Trace Capture Trace control DDR Controler DDR Transac tor Trace Capture, Trace Control and DDR Controler are Accurate models Design is a gate level netlist generating random data Data are either manually generated or come from actual compile Run million cycles on multiple designs

30 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Verification of compile SW Veloce 30 Bitstream LLSW Bitstream reader Veloce Comands Comodel SW Emulation Model Crystal Control Macro Block Configuration Block Transac tor Macro and Configuration blocks are Accurate models Bitstream is the output of actual compile flow Verify behavior of design

31 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Verification of Low Level Software 1/2 Veloce 31 Crystal Control Virtual Wire Logic Virtual Wire need a training/Calibration sequence This sequence is controled by Low Level Software Crystal Control Virtual Wire Logic Data multiplexed on serial link Example : Virtual Wire Synchronisation

32 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Verification of Low Level Software 2/2 Veloce 32 Actual LLSW Comodel SW Emulation Model Trans actor Control block in Crystal and VW block are accurate model Actual LLSW communicate with the model through comodel SW and transactor Crystal Control VW Block Control Chip Crystal Control VW Block

33 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com AVB Crystal Trigger Logic Macro Block Crystal Trigger Logic Macro Block FPGA AVB Level reduction Verification of Firmware 1/2 Veloce 33 A trigger express a condition on values coming from the design At AVB and System level it is implemented in FPGA A binary is genrerated by runtime SW to express condition Example : Trigger Reduction AVB Crystal Trigger Logic Macro Block Crystal Trigger Logic Macro Block FPGA AVB Level reduction CXB FPGA System Level reduction

34 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Verification of Firmware Veloce 34 Trigger binary SW translator Veloce Comands Comodel SW Emulation Model Control Transac tor Design is modeled as gate level netlist Trigger binary is generated by actual runtime SW Verify behavior of trigger in multiple design sequences AVB Crystal Trig ger Logi c Macro Block Crystal Trig ger Logi c Macro Block FPGA AVB Level reduction AVB Crystal Trig ger Logi c Macro Block Crystal Trig ger Logi c Macro Block FPGA AVB Level reduction CXB FPGA System Level reduction

35 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com Runtime SW Verification Veloce 35 Emulation Model Transac tor Crystal Control Macro Block Design Memories Emulator Message Bus Emulator Host Server LLSW Ressource Server Runtime Server User Message Bus UI Comodel SW Actual Runtime Server is used High level model for the HW

36 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com QUESTIONS Veloce 36

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