1. Data Acquisition Card for the Large Pixel Detector at the European XFEL 1 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory The Data Acquisition Card for the Large Pixel Detector at the European-XFEL John Coughlan, Sam Cook, Chris Day, Rob Halsall and Saeed Taghavi Science & Technology Facilities Council Rutherford Appleton Laboratory Oxfordshire, United Kingdom E-mail: john.coughlan@stfc.ac.uk

2. Data Acquisition Card for the Large Pixel Detector at the European XFEL 2 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory Contents European-XFEL Large Pixel Detector (LPD) LPD DAQ Card (FEM) FPGA Firmware 10G UDP/IP Status

3. Data Acquisition Card for the Large Pixel Detector at the European XFEL 3 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory European-XFEL DESY Hamburg Experiments to start operation in 2015

4. Data Acquisition Card for the Large Pixel Detector at the European XFEL 4 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory Eu-XFEL Bunch Structure 600  s 99.4 ms 100 ms 220 ns FEL process X-ray photons 100 fs Electron bunch trains; up to 2,700 bunches in 600  sec, repeated 10 times per second. Producing 100 fsec X-ray pulses (up to 27,000 bunches per second). XFEL ~ 27,000 bunches/s with 99.4 ms (%) emptiness Data Sampling to ASIC Analogue Memory Digitize and Serial Transmit to DAQ card

5. Data Acquisition Card for the Large Pixel Detector at the European XFEL 5 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory Large Pixel Detector 1 Mega-pixel Detector 0.5 m x 0.5 m 16 SuperModules (SM) 1 DAQ card per SM 128 ASICs per SM Delivery in 2013 16 sensor modules per SM

6. Data Acquisition Card for the Large Pixel Detector at the European XFEL 6 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory LPD ASIC Store in Pipeline during Bunch Train Readout all 3 Gain values during long 99 msec gap 130 nm IBM 16 x 32 pixels Large Dynamic range ~1 – 10**5 photons 3 x Gains stored Analogue Pipeline Memory 512 samples deep Triggered Operation Digitise @12 bits and serial readout Gains x 100 x 10 x 1 RAL Micro-Electronics Paper submitted to IEEE NSS Valencia

7. Data Acquisition Card for the Large Pixel Detector at the European XFEL 7 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory LPD Data Acquisition LPD Detector (STFC) LPD DAQ Card FEM x 16

8. Data Acquisition Card for the Large Pixel Detector at the European XFEL 8 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory XFEL Data Acquisition MicroTCA (Physics Ext) Fast Timing Signals GbE Controls LPD Detector (STFC) LPD DAQ Card FEM x 16 Clock & Controls and Veto Systems (UCL & DESY) See Poster Session XFEL Clock = 99 MHz Bunch Clock = 4.5 MHz Train Rate = 10 Hz

9. Data Acquisition Card for the Large Pixel Detector at the European XFEL 9 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory XFEL Data Acquisition AdvancedTCA MicroTCA (Physics Ext) 10 Gbps Optical (DESY) Fast Timing Signals GbE Controls LPD Detector (STFC) LPD DAQ Card FEM x 16 Train Builder System (STFC) Data Readout See Posters Session Clock & Controls and Veto Systems (UCL & DESY) See Posters Session XFEL Clock = 99 MHz Bunch Clock = 4.5 MHz Train Rate = 10 Hz 2 MByte x 512 x 10 ~10 GBytes/sec Common Systems

10. Data Acquisition Card for the Large Pixel Detector at the European XFEL 10 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory Train Builder ABCP PC Farm AB CD IJ KL MN OP EF GH 2D Detector 1 Megapixels 10 Gbps optical links Front End Electronics FEM Train Builder System Advanced TCA PC Layer 10 Gbps optical links Complete Trains FEE Fragments Train Nr % N % 1% 2% 3 % 16 Switch Data Flow X-ray Images up to 512 per train 30-100 m 10 GBytes/sec 76543217654321 Train Nr in Buffer Clock Veto Cmd XFEL Clock & Controls FEM x 16 see Poster Session “Train Builder Data Acquisition System for the European-XFEL”

11. Data Acquisition Card for the Large Pixel Detector at the European XFEL 11 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory FEM Functional Units 128 LPD ASICs Train Builder C&C Dual PPC Virtex 5 FX100T PC FMC ANSI/VITA57 JTAG

12. Data Acquisition Card for the Large Pixel Detector at the European XFEL Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory FEM Clock Domains

13. Data Acquisition Card for the Large Pixel Detector at the European XFEL 13 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory LPD FEM Side 1 Virtex 5 FX100T FPGA 2 x Samtec Backplane Connectors 240 way SP3 I/O SP3 CFG XFEL C&C SRAM FLASH GbE Slow Controls FEM side 1 128 LPD ASICs

14. Data Acquisition Card for the Large Pixel Detector at the European XFEL 14 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory LPD FEM Side 1 XFEL DAQ Virtex 5 FX100T FPGA 2 x Samtec Backplane Connectors 240 way SP3 I/O SP3 CFG XFEL C&C SRAM FLASH GbE Slow Controls FEM side 1 LPD Dual 10 Gbps SFP+ FPGA Mezzanine Card FMC ANSI/VITA 57 (DESY) Train Builder

15. Data Acquisition Card for the Large Pixel Detector at the European XFEL 15 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory LPD FEM Side 2 DDR2 SODIMM 1 GByte Memory Compact Flash configuration RS232 cable JTAG cable FEM side 2 XFEL DAQ LPD PCB 16 layers (8 signal)

16. Data Acquisition Card for the Large Pixel Detector at the European XFEL 16 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory FPGA Units Overview ASIC Slow Ctrl ASIC Fast Commands SP3 Confign FPGA ASIC Data Rx DDR2 Memory Controller 10GbE Link UDP/IP GbE/ RS232 Timing & Veto SP3 Top I/O (80%) SP3 I/O FPGAs Virtex5 Main FPGA LPD XFEL DAQ Clock & Controls C&C Emulation ASIC Simulated Data DATA CTRLS 128 ASICs PC Virtex 5 FX100T FPGA (Dual PPC cores) Local Link Local Link Processor Embedded

17. Data Acquisition Card for the Large Pixel Detector at the European XFEL 17 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory FPGA ASIC Unit ‘99’ MHz PLL Master Clock ASIC Fast Serial Interface Master Cmd Strm Master Sync, Trigger, Readout, status… Timing System Interface Computer System Interface ASIC Slow Serial Interface PLB ASIC Fast Data Interface Local Link OUTPUT ~ 640 MByte/s 128 Emulation Hit List for Veto Mode Clock State Machine INPUT ~ 1.5 GBytes/s VETOS CONFIG Clock & Controls 1 of 3 Gain Selection ASIC Clock DATA

18. Data Acquisition Card for the Large Pixel Detector at the European XFEL 18 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory Testing Bench with LPD ASIC FEM with DESY 10G FMC Extender Card with Nat Inst cable Single ASIC module FPGA dev board with C&C test adapter PC with 10GbE NIC running MatLab software Pseudo-Random Data Image Power and Cooling MatLab UDP RS232 control

19. Data Acquisition Card for the Large Pixel Detector at the European XFEL 19 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory FPGA 10G UDP/IP Firmware Module 10GbE UDP/IP Firmware Module Xilinx “Local Link” Interfaces to Power PC DDR2 Memory Controller And ASIC Data Receiver Module Chelsio T4 NIC Quad 10G SFP+ x8 PCIe Gen2 UDP API “Direct Driver” to App Memory 10G Test Bench

20. Data Acquisition Card for the Large Pixel Detector at the European XFEL 20 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory LPD Software FPGA Embedded System Dual PPC Cores Core #1 for DDR2 DMA Memory Controller Core #2 Running Xilkernel / lightweight IP stack (LwIP) Have TCP control protocol over TCP/IP Control resources on board (GPIO, I2C, EEPROM) FEM support library library & applications (C & Python) for rapid prototyping developed GDA GUI based controls system as used on Diamond Light Source at Rutherford FPGA Embedded Software Xilinx EDK PC Software

21. Data Acquisition Card for the Large Pixel Detector at the European XFEL 21 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory FEM Status 4 FEM cards assembled. All passed JTAG without error. All components pass functional tests. FPGA 10G UDP/IP working with DESY FMC to PC NIC. Clock and Controls and Slow Controls GbE working. FEM reading out images from LPD ASIC module. Emulating Train Builder interface with FPGA dev boards. Manufacturing another 20 FEMs for LPD (and Medipix) Test FEM in LPD SuperModule in 2012 Ready for LPD 1 Mega-pixel detector 2013

22. Data Acquisition Card for the Large Pixel Detector at the European XFEL 22 Tuesday 28 th September 2011, TWEPP Vienna Presented by John Coughlan STFC Rutherford Appleton Laboratory Thank you Acknowledgements: LPD Collaboration (STFC Rutherford Appleton Laboratory) M. Zimmer, I. Sheviakov (DESY) C. Youngman (XFEL) Posters Session: “Design of the Train Builder Data Acquisition System for the European-XFEL” John Coughlan et al. “Design and Development of Electronics for the EuXFEL Clock and Control System” Erdem Motuk et al.