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Recent progress in the Development of a B- Factory Monolithic Active Pixel Detector Samo Stanič for the Belle Pixel Group H. Aihara 5, M. Barbero 1, A.

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Presentation on theme: "Recent progress in the Development of a B- Factory Monolithic Active Pixel Detector Samo Stanič for the Belle Pixel Group H. Aihara 5, M. Barbero 1, A."— Presentation transcript:

1 Recent progress in the Development of a B- Factory Monolithic Active Pixel Detector Samo Stanič for the Belle Pixel Group H. Aihara 5, M. Barbero 1, A. Bozek 4, T. Browder 1, M. Hazumi 3, J. Kennedy 1, N. Kent 1, S. Olsen 1, H. Palka 4, M. Rosen 1, L. Ruckman 1, S. Stanič 2, K. Trabelsi 1, T. Tsuboyama 3, K. Uchida 1, G. Varner 1 and Q. Yang 1 1 University of Hawaii, USA, 2 Nova Gorica Polytechnic, Slovenia, 3 High Energy Accelerator Research Organization (KEK), Japan, 4 H. Niewondiczanski Institute of Nuclear Physics, Poland, 5 University of Tokyo, Japan 10 th European Symposium on Semiconductor Detectors Wildbad Kreuth, 2005/06/13

2 Samo Stanič - Wildbad Kreuth - 2005/6/13 1 ~1 km in diameter Mt. Tsukuba KEKB Belle  / K L detection 14/15 lyr. RPC+Fe Central Drift Chamber small cell +He/C 2 H 5 CsI(Tl) 16X 0 Aerogel Cherenkov cnt. n=1.015~1.030 Silicon Vertex Detector TOF counter SC solenoid 1.5T 8 GeV e - 3.5 GeV e + Belle detector 8 GeV e - x 3.5 GeV e + L peak > 1.5 x 10 34 cm -2 sec -1 (world record peak luminosity) Recorded integrated luminosity of about 400 fb -1 ! KEKB / Belle started operation in 1999 Belle Experiment at KEKB Collider

3 Samo Stanič - Wildbad Kreuth - 2005/6/13 2 Conventional solutions (Si strips) will not work… 2. Improvement of impact parameter resolution ~10%~4% ~2% Present Belle SVD2 Motivation SuperKEKB luminosity increase: L~1.5 x 10 34 → L~5 x 10 35 cm -2.s -1 1. Reduce SVD occupancy Present : layer 1 of SVD ~10% occupancy / 200 Krad.yr -1 Upgrade: Super-Belle ~ 20 – 50 x (?) expected background increase

4 Samo Stanič - Wildbad Kreuth - 2005/6/13 3 1.Low occupancy 2.Fast Readout Speed 3.Radiation Hardness 4.Thin Sensor 5.Full-sized detector prototype Natural alternative - Pixel type sensor Technology Choice CAP1 – basic functionality CAP2 – pipelined readout CAP3 – full-size/speed PVD1.0 Jun. 2004 @ KEK T943 Dec. 2004 @ FNAL MAPS XTEST2, LHC hybrid pixels Autumn 2005 (expected)  Near Term (SVD2 Layer 1 drop-in)  IR upgrade Preliminary Design Report Requirements R&D steps Prototypes

5 Samo Stanič - Wildbad Kreuth - 2005/6/13 4 Belle Pixel Sensor Evolution PVD1.0 CAP3 CAP2 pipelined readout full-size/speed CAP1 basic functionality 2005 2004 2003 time final detector technology choice

6 Samo Stanič - Wildbad Kreuth - 2005/6/13 5 Candidate: Monolithic Active Pixel Sensor Current DSSD Because of large capacitance, need for thick DSSDs -- MAPS can be made VERY thin 300  m MAPS 10  m Key Features Thermal charge collection (no HV) Thin - reduced multiple-scattering,  conversion, background  target NO bump bonding – fine pitch possible (8000x geometrical reduction) Standard CMOS process - “System on Chip” possible

7 Samo Stanič - Wildbad Kreuth - 2005/6/13 6 Continuous Acquisition Pixel (CAP) Concept ADC & storage Pixel Array: Column select – ganged row read High-speed Analog read-out Low power – only significant draw at readout edge Pixel Array of pixels time Vreset Δv typ α I leak Δv sig α Q signal Integration time t fr2 t fr1 reset Based on 3 transistor cell V_Q_integr Source follower buffering of collected charge Restores potential to collection electrode Reset Vdd Collection Electrode Gnd M1 M2 M3 Row Bus Output

8 Samo Stanič - Wildbad Kreuth - 2005/6/13 7 Correlated Double Sampling (CDS) ( - ) Frame 1 - Frame 2 = 8ms integration - Leakage current Correction ~fA leakage current (typ) ~18fA for hottest pixel shown Can readout/process @ 20Hz ~ 16% live time (CAP1!) Self-Triggering mode Hit candidate!

9 Samo Stanič - Wildbad Kreuth - 2005/6/13 8 CAP1: basic operation confirmed in a beam-test experiment All LVDS digital I/O 300-600Mbaud link Pixel chip: 132x48=6336 channels The 4 F2 boards On board ADC ~1mm x 3mm Pion Beam X-Y stages

10 Samo Stanič - Wildbad Kreuth - 2005/6/13 9 CAP1/2 system overview Front-End board CAP 4 Front-End boards Back-End board Highlights: Front-End board: MUX, ADC, serializer, CPLD Back-End board: cPCI RAM, 5 CPLDs, CPU Test pixel in Marker 132 col 48 row 48 → 12 CTRL MUX ADC Serializer Power supply & control lines (LVDS, RJ45) 1 serial signal (LVDS, RJ45) F2 BUF RAM CTRL BUSCPU Data Acquistion

11 Samo Stanič - Wildbad Kreuth - 2005/6/13 10 Correlated hits in all 4 layers

12 Samo Stanič - Wildbad Kreuth - 2005/6/13 11 Hit resolution measurement L3 L4 L2 “ hit ” Residuals for 4GeV/c pions: < 11  m (in both planes) (in mm) 250  m Si 1mm plastic 1mm Alumina substrate 3.4 cm 3.6 cm4.6 cm x-plane z-plane

13 Samo Stanič - Wildbad Kreuth - 2005/6/13 12 Radiation damage Belle CAP1 Prototype IEEE Trans. Nucl. Sc. 48, 1796- 1806,2001 Fully annealed

14 Samo Stanič - Wildbad Kreuth - 2005/6/13 13 Peak pixel S/N prediction Extrapolation from upper edges of Eid et al.

15 Samo Stanič - Wildbad Kreuth - 2005/6/13 14 CAP2 – Pipelined operation 8 deep mini-pipeline in each cell Pixel size 22.5  m x 22.5  m 3-transistor cell 132x48=6336 channels 50688 samples TSMC 0.35  m 132 x 48 10  s frame acquisition speed achieved!

16 Samo Stanič - Wildbad Kreuth - 2005/6/13 15 CAP3 – Full scale pipelined prototype 36 transistors/pixel 5 metal layers 5 sets CDS pairs TSMC 0.25  m Process 5-deep double pipeline

17 Samo Stanič - Wildbad Kreuth - 2005/6/13 16 CAP3 - sensor layout 928 x 128 pixels = 118,784 ~4.3M transistors ! 21 mm Active area 20.88 mm >93% active without active edge processing 3 mm

18 Samo Stanič - Wildbad Kreuth - 2005/6/13 17 CAP3 readout F3 board CAP3 Laboratory testing of the F3 frontend readout board is under way Working on the firmware ADC/LVDS Ampl CAP3 Bonds

19 Samo Stanič - Wildbad Kreuth - 2005/6/13 18 System setup for CAP3 sensor MC1 card Serialized data out from the MC1 card and control signals to the MC1 card through RJ- 45 connectors. CAP3 F3 BE MOBCADS

20 Samo Stanič - Wildbad Kreuth - 2005/6/13 19 CAP3 DAQ New CPU card for DAQ: from a slow 300 MHz PIII processor for CAP1/CAP2 to 2.2 GHz Pentium4 and neat 2.5” 100Gb on-board disk (using Fedora Core 3 ) → boost to the data acquisition. 2.2GHz P4 100GB disk RAM

21 Samo Stanič - Wildbad Kreuth - 2005/6/13 20 CAP3 system overview All these components sit on movable table

22 Samo Stanič - Wildbad Kreuth - 2005/6/13 21 CAP3 based full detector concept e-e+ # of Detector / layer ~ 32 End view 128 x 928 pixels, 22.5  m 2 ~120 Kpixels / CAP3 0.25  m process CAP3 5-layer flex PIXRO1 chip Pixel Readout Board (PROBE) Side view Half ladder scheme Double layer, offset structure r~8mm Length: 2x21mm ~ 4cm 17 o 30 o r~8mm

23 Samo Stanič - Wildbad Kreuth - 2005/6/13 22 “Fast” Belle SVD2 L1 upgrade option ~10%~4% ~2% Replace Layer 1 with CAP3 pixels Mechanically identical (drop in) CAP3 Flex

24 Samo Stanič - Wildbad Kreuth - 2005/6/13 23 Belle SVD L1 upgradeCAP3 Flex 4 x 9 = 36 CAP3 / L1 ladder 6 ladders/L1 layer ~26M Channels total Scaling current SVD L1 * 4 background ~ few kBytes/event R=7mm configuration: 6.6M channels SVD L1 * 40 background ~ few 100kBytes/event With L3 track match: ~few 10kBytes/event

25 Samo Stanič - Wildbad Kreuth - 2005/6/13 24 Summary: Critical R&D Milestones 1.Readout Speed 2.Radiation Hardness 3.Thin Detector 4.Full-sized detector 100kHz frame rate, 10kHz L2 accept >= 20MRad <= 50  m, double layer Span acceptance (reticle limit) 10  s frame acquisition OK (CAP2), CAP3 to test 100  s frame readout Leakage current OK (CAP2), q collection efficiency TBD 50  m mechanical dummies, CAP3 to be thinned (SNF) CAP3 fabricated – performance evaluation under way

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