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Unit III Design for Testability

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Presentation on theme: "Unit III Design for Testability"— Presentation transcript:

1 Unit III Design for Testability

2 Syllabus Design for Testability – Ad-hoc design – generic scan based design – classical scan based design – system level DFT approaches.

3 Validation and Test of Manufactured Circuits
Goals of Design-for-Test (DFT) Make testing of manufactured part swift and comprehensive DFT Mantra Provide controllability and observability Components of DFT strategy Provide circuitry to enable test Provide test patterns that guarantee reasonable coverage

4 Design for Testability
Exhaustive test is impossible or unpractical

5 Test Approaches Ad-hoc testing Generic Scan-based Design
Classical scan Designs Problem is getting harder increasing complexity and heterogeneous combination of modules in system-on-a-chip. Advanced packaging and assembly techniques extend problem to the board level

6 Ad Hoc Design for Testability Techniques
Test points Initialization Monostable Multivibrator Oscillators and clocks Partitioning of counters and shift registers Partitioning of large combinational circuits Logical Redundancy Global feedback paths

7 Test Points Method of Test Points: Block 1 is not observable,
Block 2 is not controllable Block 1 Block 2 Improving controllability and observability: OP 1- controllability: CP = normal working mode CP = controlling Block 2 with signal 1 Block 1 1 Block 2 CP OP 0- controllability: CP = normal working mode CP = controlling Block 2 with signal 0 Block 1 & Block 2 CP

8 Test Points (contd.) Method of Test Points: 1 & CP1 CP2 MUX CP1 CP2
Block 1 is not observable, Block 2 is not controllable Block 1 Block 2 Improving controllability: Normal working mode: CP1 = 0, CP2 = 1 Controlling Block 2 with 1: CP1 = 1, CP2 = 1 Controlling Block 2 with 0: CP2 = 0 Block 1 1 & Block 2 CP1 CP2 Normal working mode: CP2 = 0 Controlling Block 2 with 1: CP1 = 1, CP2 = 1 Controlling Block 2 with 0: CP1 = 0, CP2 = 1 Block 1 MUX Block 2 CP1 CP2

9 Monostable Multivibrator

10 Oscillators and Clocks

11 Partitioning of Registers

12 Partitioning of Large Combinational circuits

13 Partitioning of Large Combinational circuits (contd.)

14 Generic scan-based Design
Full Serial Integrated Scan Isolated Serial Scan Nonserial Scan

15 Full Serial Integrated Scan

16 Isolated Serial Scan

17 Isolated Serial Scan (contd.)

18 Non-serial Scan

19 Level-Sensitive Scan Design (LSSD)

20 System-Level DFT Approaches
System-level Busses System-level Scan paths

21 System-level Busses

22 System-level Scan paths

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