1. An Ultra Low Power System Architecture for Sensor Network Applications Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Prof. Gu-Yeon Wei, Prof. David Brooks Division of Engineering and Applied Sciences Harvard University Cambridge, MA

2. 2 Overview Wireless sensor networks (WSN) are constrained by energy consumption Goal: Average power consumption <100 µW enables energy scavenging methods Our architectural approach: Holistic approach Event-driven architecture Modular hardware accelerators Fine-grain power management In the implementation phase

3. 3 Outline What are sensor networks? Project motivation and design constraints Event-driven architecture Performance and power estimates Conclusion and future work

4. 4 Sample Application Space Monitoring Apps Structural/Earthquake/Weather/Habitat monitoring Building/Border/Battlefield detection Road/traffic monitoring Medical Apps Long-term health monitoring Untethered Pulseox Sensors Business Applications Supply Chain Management Expired/Damaged Goods Tracking Automatic Checkout Systems

5. 5 Example App: Great Duck Island Great Duck Island (GDI), Maine - (UC Berkeley) Gather temp, humidity, IR readings from Leach's Storm Petrel burrows and weather station motes Determine occupancy of nests to understand migration patterns Total of 150 nodes deployed in 2003, over 650,000 observations taken Performance Requirements are Low Samples taken and transmitted once every 5 min Power consumption limited lifetime of deployment R. Szewczyk et al. An Analysis of a Large Scale Habitat Monitoring Application. ACM Conference on Embedded Networked Sensor Systems (SenSys), 2004. Single Hop Network Multi-Hop Network

6. 6 Example Sensor Network Node Small Form Factor Battery Operated Wireless Communication and Adhoc Networking Interface to Various Sensors Programmable CPU Low Power Low Throughput TinyOS for Event Driven Mica2 Mote – Designed by UC Berkeley, Manufactured by Crossbow

7. 7 Energy is the primary limitation CPU ModeCurrent @3VRadio ModeCurrent @3V Active8.0 mAReceive7.0 mA Idle3.2 mATransmit Min Power3.7 mA Standby216 µATransmit Max Power21.5 mA Power-save110 µASensor Board0.7 mA Mica2 Power Consumption Measured by component Not the complete picture, how is power consumed in an application? V. Shnayder, M. Hempstead, B. Chen, G. Werner-Allen, M. Welsh. Simulating the Power Consumption of Large-Scale Sensor Network Applications. (SenSys'04).

8. 8 Application-level Power Analysis Total energy consumption per component of “Surge”, a multi-hop routing application, run for 60 sec on the Mica2 mote. Can be decreased at application and protocol levels however this requires more CPU computation Due to General Purpose architecture of CPU Requires software overhead to run TinyOS Design Goal: Average Power consumption of < 100 µW to enable energy scavenging methods. Where should design energy be focused to decrease energy consumption?

9. 9 Regular Application Behavior Timer Interrupt Collect Sensor Data Prepare Message Send Radio Message Sense and Transmit Message Arrives Decode Message Search Routing Table Resend Radio Message Receive and Forward Abstract ViewExample - GDI Every 5 min Burrow Occupancy - infrared - humidity - Pack data in packet - Calculate checksum - wait for acknowledgement

10. 10 Key goals of our architecture Energy Efficiency Flexibility/Programmability OUR SYSTEM General Purpose CPU Remove Software Overhead ASIC Retain Programmability Event-driven computation Hardware accelerators for power-efficiency Exploit regular operations Optimize for sensor net workloads Modular design Fine-grain power management

11. 11 Abstract view of architecture General Purpose Microcontroller Radio Transceiver Sensors Event Processor Slave Blocks Shared Memory

12. 12 Detailed view of architecture Regular events mapped solely to EP and slaves Micro Controller included for irregular events Slaves provide application specific HW All resource usage is explicit Micro Controller Event Processor System Bus Interrupt Power Ctrl Addr/Data SRAM Sensors Radio Message Processor Data Filter Timer Addr/Data

13. 13 Event Processor Interrupts invoke EP interrupt service routines 8 instructions 4 power control/control transfer 4 read/write/transfer data to devices

14. 14 App. Example: Sense + Transmit Timer Interrupt Collect Sensor Data Prepare Message Send Radio Message System Initialization/Reprogram Configuration written to memory and timer Micro Controller Event Processor System Bus Interrupt Power Ctrl SRAM Sensors Radio Message Processor Data Filter Timer Addr/Data

15. 15 Example: Sense + Transmit (2) Timer Interrupt Collect Sensor Data Prepare Message Send Radio Message Pseudo Code : SWITCHON TRANSFER SWITCHOFF WRITEI TERMINATE; Micro Controller Event Processor System Bus Interrupt Power Ctrl Addr/Data SRAM Sensors Radio Message Processor Data Filter Timer Addr/Data

16. 16 Example: Sense + Transmit (3) Pseudo Code : SWITCHON TRANSFER SWITCHOFF WRITEI TERMINATE; Timer Interrupt Collect Sensor Data Prepare Message Send Radio Message Micro Controller Event Processor System Bus Interrupt Power Ctrl SRAM Sensors Radio Message Processor Data Filter Timer Addr/Data

17. 17 Example: Sense + Transmit (4) Pseudo Code SWITCHOFF TERMINATE; Timer Interrupt Collect Sensor Data Prepare Message Send Radio Message Micro Controller Event Processor System Bus Interrupt Power Ctrl SRAM Sensors Radio Message Processor Data Filter Timer Addr/Data

18. 18 Example: Sense + Transmit (5) System Idle Timer Interrupt Collect Sensor Data Prepare Message Send Radio Message Micro Controller Event Processor System Bus Interrupt Power Ctrl SRAM Sensors Radio Message Processor Data Filter Timer Addr/Data

19. 19 Implementation Process technology study (see paper) Does Moore’s Law help us? Leakage power increasing concern Tradeoff active power and leakage power Architectural enables low power circuit techniques Fine-grain power management – VDD gating Simple Circuit Implementation Synchronous design VDD roughly 2V T Performance Target: 100 kHz Possible to use less common circuit design styles (subthreshold, asynchronous)

20. 20 Initial Results Developed performance model for system architecture in SystemC (~8K lines of code) GP microcontroller, event processor, slave blocks, radio Power Model VHDL for Event Processor + Key Blocks Custom design (SRAM, CAM) 0.25 µm Process Technology Workload Analysis and early comparison to other architectures included in the paper

21. 21 Performance Comparison Roughly 10x cycle-reduction justifies 100KHz clock speed

22. 22 Power estimates Unknown blocks: GP microcontroller, busses, off-chip interfaces

23. 23 Conclusion/Future work Wireless Sensor Networks provide unique opportunities for low power, low throughput design Architecture meets design goals Less than 100 µW average power consumption Event Processor provides event handling in HW HW slaves provide application specific processing for regular tasks Fits sensor network application characteristics Implementation phase of first chip Stay Tuned!