1. Chapter 10. Phase-Locked Loops
Different Applications of PLLs:

2. Phase-Locked Loop Applications

3. Phase-Locked Loop Applications
Figure Phase-locked loop applications.

4. The Phase Detector
A simple analog phase detector is shown in Figure 10-2a. Consider the phase detector as a simple switch, as illustrated in Figure 10-2b.
The signal with frequency fo simply opens and closes the (diode) switch. If fi ≠ fo, then the circuit behavior is that of a mixer producing the sum and difference frequencies.

5. The Phase Detector
The capacitors shown are chosen to bypass fi, fo, and fi + fo, and therefore only the beat (fi - fo) signal is seen at vd. After the loop is locked, fo will be exactly equal to fi.
A phase difference between the two input signals results in a dc voltage Vd, which is proportional to the phase difference, qe = qi - qo .

6. The Phase Detector Figure 10-2. (a) Analog phase detector.
(b) Simpified model.

7. The Phase Detector
A mixer performs the mathematical function of multiplication. Thus for sinusoidal inputs,
When phase-locked, wo = wi, the second harmonic term, Asin[2wot + qo + qi], is filtered out, leaving
Vd = Asin(qi - qo) (10-1)
This voltage is directly proportional to the input signal amplitude and the phase error qe if the signal amplitude is held constant.
Indeed, for small qe , this transfer function is linear as seen in Figure 10-3.

8. The Phase Detector
Figure Analog phase detector characteristic-output voltage versus input phase difference.

9. Figure 10-4. Phase detector waveforms.
The Phase Detector
Figure Phase detector waveforms.

10. The Phase Detector
Figure 10-4 helps to show the results graphically as oscilloscope measurements.
When the signals are out of phase by 90o as in part (a),
a zero dc output results;
If the phase is slightly advanced as in part phase as in part (b), a small negative dc output is produced;
When the signals are exactly in phase as in part (c), the result is a dc output proportional to the fi signal level--exactly the kind of signal that is needed for a lock indication in telephone touchtone decoders or AGC in coherent receivers.

11. Phase Detector Gain
The PD characteristic is a continuous sinusoid repeating every 2p radians. Also, during the tracking mode, operation is limited to the portion of the curve between +p/2 where |qe| < p/2.
For sinusoidal inputs it is clear from Figure 10-6 that the slope of the phase detector characteristic curve,
Vd = Asinqe (10-2) is not constant.
In fact, it rises with a maximum slope at qe = 0, and levels off to a slope of zero (no gain) at qe = p/2 radians.

12. Phase Detector Gain
The peak voltage A is the volts-per-radian gain of this phase detector because the tangents to the peak and the PD curve at qe = 0 intersect at one radian, as seen in Figure 10-6.
Therefore the gain of the analog phase detector is
kf = A (volts/radian) (10-3)

13. Phase Detector Gain Figure 10-6. Sinusoidal characteristic of
analog phase detector.

14. Phase Detector Gain
If the input signals are both square-waves, the phase detector characteristic will be linear, as illustrated in Figure 10-7.
The gain of this circuit is constant over the range of input qe = +p/2 and is given by
kf = Vd/qe = A/(p/2).
That is,
kf = 2A/p (volts/radian) (10-4)

15. Phase Detector Gain Figure 10-7. Phase comparator characteristic
for square-wave inputs.

16. Phase Detector Gain
Figure 10-8 is typical of balanced integrated circuit implementations. This circuit is also used as a balanced AM modulator for producing double-sideband/suppressed-carrier signals and consists of differential amplifiers.
The oscillator input polarity determines which differential pair conducts, while the signal input determines whether Rc1 or Rc2 receives the current.
The output voltage will be the difference between i1Rc1 and i2Rc2 .

17. Phase Detector Gain
Figure 10-8 Integrated circuit balanced detector.

18. Digital Phase (Timing) Comparators
Digital phase detectors can be realized using an exclusive-OR (Figure 10-9) or an edge-triggered set-reset flip-flop (RS-FF) circuit.
The exclusive-OR output Y is low when both inputs are high or low; otherwise Y is high, indicating “or.”
The output is smoothed (integrated) to produce Vd. The exclusive-OR requires symmetrical square wave inputs,
which may become a system problem, whereas the edge-triggered RS-FF works well with pulses.

19. Digital Phase (Timing) Comparators
Figure Digital implementation of phase detector using an exclusive-OR gate.

20. Digital Phase (Timing) Comparators
As illustrated for the circuit of Figure 10-10, the RS-FF phase detector can produce a linear PLL over a full qe range of 2p rad, which is twice that for the other phase detectors.
The problem with using digital phase detectors in sensitive communication receiver applications is in the difficulty of filtering the sharp impulses and their harmonics to prevent radio-frequency interference (RFI).

21. Digital Phase (Timing) Comparators
Figure Digital implementation of phase detector using a set-reset flip-flop.

22. Amplifiers
Figure Operational amplifiers increase PLL loop gain.

23. Amplifiers
The second loop component is an amplifier commonly referred to as the dc amp. Its function is to increase the loop gain by amplifying the phase detector output voltage.
Figure shows three voltage amplifiers and their gain parameter kA = AV (volts out/volts in).
The bandwidth of the dc amp must be very high compared to the loop bandwidth or loop instability will result--even to the point of oscillation due to excessive phase shift around the loop, which would produce positive (regenerative) feedback.

24. Voltage-Controlled Oscillator (VCO)
Figure Tuning diode control of free-running multivibrator.

25. Voltage-Controlled Oscillator (VCO)
The frequency of the free-running multi-vibrator circuit of Figure is controlled by the variable reactance of D1 and D2. In IC implementations, D1 and D2 are realized by reverse-biased collector junctions.
It should be noted that the control voltage must not exceed VE + 0.5V + ve, where ve is the positive peak of the oscillator signal across RE and 0.5V causes forward bias of the silicon diodes.The input-output characteristic for the VCO is shown in Figure

26. Voltage-Controlled Oscillator (VCO)
Figure VCO characteristic.

27. BASIC LOOP BEHAVIOR- Locking the loop
Start with switch open (Figure 10-14) and a signal generator with frequency fi connected to the input.
With fi not equal to the free-running frequency (fFR), the phase detector will produce the sum and difference frequencies.
The loop (low-pass) filter filters out the sum frequency (fi + fFR), fi , and fFR, while the difference (fi - fFR)--the beat between the signal generator and VCO--is allowed to pass through.
The beat is amplified and seen as on an oscilloscope. As the generator frequency is varied to bring fi closer to fFR, the beat frequency gets lower and lower. This is illustrated in Figure

28. BASIC LOOP BEHAVIOR- Locking the loop
Figure PLL block diagram.

29. BASIC LOOP BEHAVIOR- Locking the loop
Figure Beat-frequency output at Vo with loop open. The input generator frequency is being varied from fi < fFR to fi > fFR.

30. Acquisition
In Fig , with the VCO input grounded and Vo = 0, measurements will show that fi = fFR.
However, if fi ≠ fFR, then the beat is observed at Vo. When the switch is closed, the beat-frequency signal at Vo will cause the VCO frequency fo to change.
If the voltage is large enough (high loop gain) and the filter bandwidth wide enough, then the VCO will be deviated from fFR and lock at the instant that fo = fi .

31. Acquisition
The amount by which the VCO frequency must be changed is Df = fi - fFR. The time required for the loop to lock depends on the type of loop and loop dynamics.
For the simplest PLL with no loop filter, this acquisition time is on the order of 1/kv seconds.
Also, the range of fi over which the loop will lock, the lock range, is equal to the hold-in range for the simple PLL.

32. Locked Loop: The Tracking Mode
When the loop is locked we know that fo = fi. Only a phase difference between the signal and the VCO can exist.
This phase difference qe = qi - qo is called the static (dc) phase error.
qe is the input to the phase detector when the loop is locked and is required in order for the phase detector to produce a dc output voltage Vd .
The dc output voltage Vd, when amplified by the dc amplifier, will produce exactly enough Vo to keep the VCO frequency deviated by Df.

33. Locked Loop: The Tracking Mode
If fi increases, then Df increases and qe must increase in order to provide for more Vo to keep the VCO tracking fi.
The definition of locked is that fi = fo and the loop will track any change in fi.
Any subsequent shift of qi or qo will be tracked-out so that only qe remains.

34. Hold-In Range
The range of frequencies for fi over which the loop can maintain lock is called hold-in range.
Assuming that the amplifier does not saturate and the VCO has a wide frequency range, the phase detector characteristic limits the hold-in range.
It should be clear from the phase detector characteristics (Figs 10-6 and 10-7) that, as the static phase error increases due to increasing fi ,
a limit for Vd is reached beyond which the phase detector cannot supply more voltage for VCO correction.

35. Hold-In Range
The phase detector simply cannot produce more than A volts. The total range of Vd is ±A = 2A, so that the total range of qe is p radians.
From Equ. (10-7), the minimum to maximum input frequency range, fi(max) - fi(min) = DfH, will be
DfH = pkL or DfH = kv/ (10-9)
The edge-triggered R-S flipflop phase comparator of Figure 10-9 can provide twice this, DfH = kv.

36. Loop Gain and Static Phase Error
The locked PLL is seen in Figure The phase comparator develops an output voltage Vd in response to a phase difference between the reference input and the VCO.
The transfer gain kf has units of volts/radian of phase difference. The amplifier shown is wideband with a voltage gain of kA volts/volt (dimensionless). Thus, Vo = kAVd.

37. Loop Gain and Static Phase Error
Figure PLL in tracking mode (locked).

38. Loop Gain and Static Phase Error
The VCO free-running frequency is fFR. The VCO frequency fo will change in response to an input voltage change.
The transfer gain ko has units of kHz/V. The loop gain for this system is simply the gain of each block multiplied around the loop,
thus
kL = kf.kA.ko (10-6)
The units of kL are (V/rad).(V/V).(kHz/V) = kHz/rad.

39. Loop Gain and Static Phase Error
Assume that a signal with frequency fi is an input to the phase detector, and the loop is locked.
If the frequency difference before lock was Df = fi - fER, then a voltage Vo = Df/ko is required to keep the VCO frequency equal to fi.
So the phase comparator must produce Vd = Vo/kA = Df/kAko, and the static phase error qe = qi - qo must be qe = Vd/kf.

40. Loop Gain and Static Phase Error
Combining gives qe = Df/ kfkAko = Df/kL. This is a fundamental equation for the PLL in phase lock;
qe = Df / kL (10-7)
In many computations the loop gain must be in units of rad/sec rather than in kHz/rad The conversion is made using 2p radians/cycle.
Hence, loop gain is also given by
kv = 2pkfkAko (10-8)
in unit of sec-1 or radians/second.

41. Loop Gain and Static Phase Error
Example: Figure provides enough information to analyze the static behavior of a phase-locked loop.
1. Determine kA for the op-amp.
2. Calculate the loop gain in units of sec-1 and in dB
(at w = 1 rad/s).
3. With S1 open as shown, what is observed at Vo
with an oscilloscope?
4. When the loop is closed and phase-locked, determine (a) the VCO output frequency, (b) static phase error at phase comparator output, (c) Vo (is this rms, pk-pk, or what?).
5. Determine the hold-in range DfH.
6. Determine A, the maximum value of Vd.

42. Loop Gain and Static Phase Error
Figure Example PLL.

43. Loop Gain and Static Phase Error
Solution:
1. kA = (Rf/R1) + 1 = 4kW/1kW + 1 = 5.
2. kL = kf kA ko = 0.1 V/rad x 5 x (-30 kHz/V)
= -15x103 (Hz/rad).
Then, kv = 15x103cycles/s-rad x (2p rad/cycle)
= sec-1,
and kv(dB) = 20 log kv = 20.log(94.3x103)
= 99.5dB at 1 rad/s.
3. Vo will be a sinusoidally varying voltage with a frequency of |fi – fFR| = 10 kHz.
This assumes that a very small capacitor internal
to the phase comparator filters out fo, fi and fo+fi.

44. Loop Gain and Static Phase Error
4(a). When the loop is locked, fo = fi = 100 kHz by definition of locked, and only a phase difference can exist between the input signal and VCO.
This phase difference qe is the loop-error signal (static phase error) which results in Vd at the detector output and, when amplified by kA, provides enough voltage Vo to make the VCO frequency be exactly equal to fi.

45. Loop Gain and Static Phase Error
4(b). The free-running frequency of the VCO is 110 kHz.
In order for the VCO to equal 100 kHz, the VCO
input voltage must be
Vo = (100 kHz –110 kHz)/ko
= 10 kHz/(-30 kHz/V) = 0.33Vdc.
Then, because kA = 5, Vd must be
Vd = 0.33V/5 = V.
Finally, qe = Vd/kf = V/0.1V/rad = rad.
Once again, we have derived the basic relationship,
qe = Df/kL = (fi - fER)/kL
= -10 kHz/(15x103 Hz/rad)
= rad.

46. Loop Gain and Static Phase Error
4(c). The input to the phase detector (loop-locked) was determined from qe = Df/kL = rad.
Since Vd = kf qe, we have
Vd = 0.1 V/rad x rad = Vdc.
Assume that Zin of the op-amp is >> R of the loop filter, so there is no voltage drop across R.
The input to the op-amp is Vdc, so that
Vo = kAVd = 5 × Vdc = 0.33 Vdc.
This is enough to keep the VCO at 100 kHz when in fact its rest frequency is 110 kHz.

47. Loop Gain and Static Phase Error
5. When the loop is locked, how much can fi change in frequency before the loop just cannot provide enough Vo to keep the VCO at fo = fi?
Assuming that the VCO and dc amplifier don't saturate, we look at the phase detector characteristic. Clearly Vd can increase with qe until Vd --> Vmax = A, at which point qe = p/2 .
Beyond this, Vd decreases for increasing static phase error, and the phase detector simply cannot provide more output voltage to continue increasing fo, and the loop breaks lock.
The total hold-in range is +p/2, or p rad. The frequency difference between these break-lock points will be
DfH = qe(max) x kL = p x 15 kHz/rad = 47.1 kHz.

48. Loop Gain and Static Phase Error
6. At the frequency where qe = p/2, we have
Vd(max) = A.
Therefore
Vd = kfqe
= 0.1 V/rad × p/2 rad
= Vdc

49. FM and FSK Applications of PLLs
When a PLL has locked to an input signal, the VCO will follow slow changes in the input signal frequency fi.
Suppose fi increases by an amount Dfi. In order for the loop to remain locked (fo - fi), the VCO voltage must increase by DVo = Dfi/ko.
This voltage change is produced by the amplified change in Vd, which is produced by an increased phase difference, Dqe = 2pDfi/kv.

50. FM and FSK Applications of PLLs
As a specific example, suppose that an FM signal with carrier frequency fi is modulated to an index of mf = 4 by a 1-kHz sinusoid.
The carrier frequency will be deviated above and below fi by an amount Dfi = mf fm = 4 x 1 kHz = 4 kHz pk.
If this FM signal is the input to a PLL with a VCO gain of ko = 10 kHz/V and loop bandwidth 1 kHz, then the VCO input voltage Vo will be a 1-kHz sinusoid with a peak amplitude of DVo = Dfi/ko = (4 kHz pk)/(10 kHz/V) = 400 mV pk.

51. FM and FSK Applications of PLLs
Example 10-3:
A PLL with ko = kHz/V, fFR = 3.5 kHz, kf = V/rad, and kA = 5 is used as an FSK demodulator.
The input signal has fS = 4 kHz, fM =2 kHz, and the modulation is shown in Figure 10-23a.
As seen, the baud rate is 1333 bits/s and the data is …1 0 0…
Sketch accurately the PLL output Vo(t).

52. FM and FSK Applications of PLLs
Solution:
For fi = fM = 2 kHz,
Vo = Dfo/ko = (fi – fFR)/ko
= (2 kHz – 3.5 kHz)/(-0.75 kHz/V) = +2V.
For fi = fS = 4 kHz,
Vo = (4 kHz – 3.5 kHz)/(-0.75 kHz/V) = -0.67V.
The loop time constant is
t =1/kv = 1/(0.75 kHz/V).( V/rad).(5).
(2p rad/cycle) = 1/7502 = ms.
It takes ms for Vo to rise from -0.67V to 63% of the total voltage range 2V - (-0.67V) = 2.67V.
63% of 2.67V is 1.69V, so at time t, Vo = 1.69V V = 1.02V (see the plot of Vo in Figure 10-23b).

53. FM and FSK Applications of PLLs
Figure FSK input (a) and demodulated output (b) of PLL.

54. NOISE MARGIN
To get a quantitative idea of the loop noise margin, consider the results of Example 10-3 as seen in Figure 10-23b. The output voltage Vo is 2V for a transmitted MARK.
How high can Vo rise on a noise transient caused by a deviation of the MARK frequency or circuit variations of Vo before the loop breaks lock?
The static phase error when fi = fM = 2 kHz is qe = Df/kL = (2 kHz kHz)/(1.19 kHz/rad) = 1.26 rad. However, for typical phase detector's, the loop will break lock if qe exceeds p/2 = 1.57 rad.

55. NOISE MARGIN
Consequently loop transients that would cause qe to increase by 0.31 rad will result in a loss of lock.
In terms of voltages,
Vd(max) = kfqe(max)
= ( V/rad) x (1.57 rad)
= 0.5V
and Vo(max) = 5 ×0.5 = 2.5V.
Since Vo(MARK) = 2V and we-have calculated Vo (max) = 2.5V, we see that the noise margin for Vo will be Vo(NM) = 0.5 Vpk.

56. NOISE MARGIN
This can result from noise in the PLL itself, from the noise input signal-amplitude if no limiter precedes the PLL
Or from an input signal frequency deviation
(due to noise) of
Dfi(NM) = ko x Vo(NM)
= (0.75 kHz/v) x (0.5Vpk)
= 375 Hz peak noise.

57. Frequency Synthesizers
Figure PLL frequency multiplier.

58. Frequency Synthesizers
Suppose a double-conversion SSB receiver needs fixed LO frequencies at 100 kHz (for synchronous detection) and 1.6 MHz (for the second mixer), and an adjustable LO that covers MHz in steps of 0.01 MHz (for RF tuning).
The custom-tailored synthesizer in Figure provides all the required frequencies by dividing down, multiplying up, and mixing with the output of a 10-MHz oscillator.

59. Frequency Synthesizers
Figure Frequency synthesizer with fixed and adjustable output.

60. Linearized PLL Models and FM Detection
Suppose that a PLL has been tuned to lock with the input frequency fc, so Df = 0.
Suppose further that the PLL has sufficient loop gain to track the input phase f(t) within a small error e(t), so
sin(e(t)) ≒ e(t) = f(t) - fv(t).
These suppositions constitute the basis for the linearized PLL model in Fig a, where the LPF has been represented by its impulse response h(t).

61. Linearized PLL Models and FM Detection
Figure Linearized PLL modes. (a) Time domain; (b) phase; (c) frequency domain.

62. Linearized PLL Models and FM Detection
Since we’ll now focus on the phase variations, we view f(t) as the input “signal” which is compared with the feedback “signal”
to produce the output y(t).
We emphasize that viewpoint by redrawing the linearized model as a negative feedback system,
see Figure 8.3-8b.
Note that the VCO becomes an integrator with gain 2pKv while phase comparison becomes subtraction.

63. Direct Frequency Synthesizers
Figure shows a high-stability, 64-kHz master reference oscillator followed (horizontally) by a comb generator, which is a circuit used to produce a pulse rich in harmonics of the 64-kHz input signal.
A harmonic-selector filter controlled by tuning logic is tuned to the desired harmonic and rejects all other spurious outputs.
If the synthesizer consisted only of this group of blocks, the resolution would be 64 kHz because the output can be switched only to the various harmonics of the 64-kHz master reference.

64. Direct Frequency Synthesizers
Figure Direct synthesizer.

65. Direct Frequency Synthesizers
In order to improve the resolution and thereby achieve a finer separation between the possible Output frequencies, a divide-by-16 circuit is used with a comb generator and selector filter to produce 4-kHz frequency steps.
The selected frequencies from the upper and lower harmonic-select filters are mixed to produce sum and difference frequencies, and the output (switchable) filter passes the desired output frequency.

66. Direct Frequency Synthesizers
The resolution, or smallest possible discrete frequency step, is now seen to be 4 kHz.
For instance, with N1 = 2, N2 = 2, and the output filter passing the mixer sum, then
fo = 128 kHz + 8 kHz = 136 kHz.
The next higher output frequency would be 140kHz.

67. Direct Frequency Synthesizers
A multi-crystal, direct-synthesis scheme for producing the transmit carrier and two receiver local oscillators for a 23-channel citizens band transceiver is shown in Figure
This synthesizer is a crystals/oscillator scheme (a scheme is also used) and, when tuned to emergency CB channel 9 ( MHz carrier frequency), crystals 3, 7, and 11 are used.
With the receiver oscillator off, crystals 3 and 11 produce the transmit carrier: = MHz.

68. Direct Frequency Synthesizers
With the receiver oscillator on and the transmit oscillator off, the 1st and 2nd local oscillators for this double-conversion receiver are produced by the synthesis and receiver oscillators as follows: MHz from the synthesis oscillator with Xtal-3 is the 1st-LO frequency.
Thus, the 1st-IF frequency is MHz = MHz, so that FM receiver IF transformers can be used.
The receiver oscillator with Xtal-7( MHz) is the 2nd-LO, and the 2nd-IF frequency is MHz MHz = 455 kHz, so that AM receiver IF transformers can be used.

69. Direct Frequency Synthesizers
Fig Frequency synthesis (6-4-4) for
23-channel CB transceiver.

70. Phase-Locked Synthesizers
The most frequency used technique for frequency synthesis is the indirect method utilizing a voltage-controlled oscillator in a programmable PLL.
The simplest system is the one-loop synthesizer of Figure 10-39, consisting of a digitally programmable divide-by-N circuit used to divide the VCO output frequency for comparison with a stable reference source.

71. Phase-Locked Synthesizers
Figure Phase-locked frequency synthesizer.

72. Phase-Locked Synthesizers
The digitally programmable frequency-divider output, fo/N, is determined by the value of N selected by the user and is compared to the reference signal in the phase detector (PD).
When the loop is locked for a specific value of N, then fo/N = fref by definition of phase-locked; therefore the synthesizer output is
fo = Nfref (10-26)

73. Phase-Locked Synthesizers
The loop gain for the simple PLL synthesizer of Figure is
kL = kfko/N (10-27)
It is important to realize that the frequency-divider circuit reduces the loop gain so that the other loop components need to have relatively higher gain than the conventional PLL.
A more troublesome design problem, is that, as N changes, so does the loop gain. There are linearizer circuit to ameliorate this problem.

74. Phase-Locked Synthesizers
Figure shows the use of a very high frequency prescaler in a one-loop synthesizer used for push-button TV channel selection.
The VHF local oscillator (LO) frequency is > 100 MHz, so high frequency emitter-coupled logic (ECL) dividers are used to prescale the VHF signal below 1MHz, where low-cost TTL or CMOS technology can be used.
The prescaler will reduce the resolution by an amount equal to the prescale division ration P.
Hence,
Resolution = Pfref (10-28)
with a prescaler.

75. Phase-Locked Synthesizers
Figure Microprocessor-controlled
LO synthesizer for TV.

76. Phase-Locked Synthesizers
EXAMPLE:
The mp-controlled VHF LO synthesizer of Figure has a phase comparator with kf = 1 V/rad and an output impedance of 3.5kW. Determine the following:
1. fref.
2. N for the TV to receive channel 5 (fLO= MHz).
3. The synthesizer frequency resolution.
4. Loop gain and value of capacitor to compensate the loop to d = 0.5 and have the VCO frequency within 10% of its specified value in <10 ms after selection of channel 5. (The max. frequency step at the phase detector is assumed to within the loop bandwidth.)
5. What value must the VCO sensitivity be?

77. Phase-Locked Synthesizers
Solution:
1. fref = fXO/3580= kHz/3580 = kHz.
2. fo = 256fref, therefore
N = MHz/[(256)( kHz)] = 480.
3. With the prescaler, the resolution will be
Pfref = 256fref = kHz.
To prove this, change the programmable divider to N+1 = 481, and compare the new fo to the old:
fo(N+1) = kHz x 256 x 481 = 123, kHz
fo(N) = kHz x 256 x 480 = 123, kHz
Resolution: (N+1)fo – Nfo = kHz.

78. Phase-Locked Synthesizers
4. With the assumption stated, Vo must stay within relative values 0.9 and 1.1 (+10%) on the d = 0.5 curve. This is satisfied by wnt = 4.6.
With t = ts = 10 ms, we need the loop to have
wn = 4.6/10 ms = 460 rad/s.
Since d = 0.5, then wc = kv for d = 0.5.
Also , so that wn = wc = kv = 460 rad/s.
A capacitor is placed across the phase detector output (Ro= 3.5 kW) to form the lag-compensation:
C = 1/wcRo = 1/(460 x 3500) = 0.62 mF.
kv = 2pkfko/N = 460 rad/s.
Therefore, ko is required to be ko=Nkv/2pkf
= (256x480)(460)/2p(1V/rad) = 9MHz/V.

79. Translation Loops and Multiple-Loop Synthesizers
One technique used to reduce a high-frequency VCO output to reasonable frequencies without a prescaler, and to provide a frequency offset, is shown with in the dashed area of Figure
Figure is the receiver block diagram for a PLL synthesized 40-channel citizen band transceiver with delta tuning for fine-frequency adjustments.

80. Translation Loops and Multiple-Loop Synthesizers
The mixer and MHz crystal oscillator translate the VCO frequency range from MHz down to MHz for input to the programmable divider.
Notice that the reference oscillator also provides the second LO for the double-conversion receiver.

81. Translation Loops and Multiple-Loop Synthesizers
Figure PLL frequency synthesizer for a 40-channel CB transceiver.

82. Translation Loops and Multiple-Loop Synthesizers
Multiple-loop synthesizers combine all of the techniques discussed thus far.
The addition of more loops increases the resolution and frequency coverage; the individual loops also act as tracking filters to reduce unwanted mixer products and spurious output components.

83. Translation Loops and Multiple-Loop Synthesizers
Figure illustrates the basic multiple-loop synthesizer for n loops.
If the mixer outputs are filtered to pass the difference frequency and the output frequency of each VCO is lower for higher n, the synthesizer output frequency can shown to be
(10-29)
and
Resolution = fref/(M2M3…Mn) (10-30)

84. Translation Loops and Multiple-Loop Synthesizers
Figure An n-loop, multiloop synthesizer.