1. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Design rules and fabrication. n SCMOS scalable design rules. n Stick diagrams.

2. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Why we need design rules n Masks are tooling for manufacturing. n Manufacturing processes have inherent limitations in accuracy. n Design rules specify geometry of masks which will provide reasonable yields. n Design rules are determined by experience.

3. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Manufacturing problems n Photoresist shrinkage, tearing. n Variations in material deposition. n Variations in temperature. n Variations in oxide thickness. n Impurities. n Variations between lots. n Variations across a wafer.

4. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Transistor problems n Variations in threshold voltage: –oxide thickness; –ion implantation; –poly variations. n Changes in source/drain diffusion overlap. n Variations in substrate.

5. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Wiring problems n Diffusion: changes in doping -> variations in resistance, capacitance. n Poly, metal: variations in height, width -> variations in resistance, capacitance. n Shorts and opens:

6. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Oxide problems n Variations in height. n Lack of planarity -> step coverage. metal 1 metal 2

7. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Via problems n Via may not be cut all the way through. n Undersize via has too much resistance. n Via may be too large and create short.

8. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR MOSIS SCMOS design rules n Designed to scale across a wide range of technologies. n Designed to support multiple vendors. n Designed for educational use. n Fairly conservative. n http://www.mosis.com/design/rules/ http://www.mosis.com/design/rules/ n “The standard CMOS technology accessed by MOSIS is a single polysilicon, double metal, bulk CMOS process with enhancement-mode n-MOSFET and p-MOSFET devices”.

9. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR and design rules is the size of a minimum feature. Specifying particularizes the scalable rules. Parasitics are generally not specified in  units 

10. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Wires metal 3 6 metal 2 3 metal 1 3 pdiff/ndiff 3 poly 2 All wire widths are multiples of

11. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Transistors 2 3 1 3 2 3 All measures are multiples of poly diffusion substrate

12. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Vias n Types of via: metal1/diff, metal1/poly, metal1/metal2. 4 1 4 2

13. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Metal 3 via n Type: metal3/metal2. n Rules: –cut: 3 x 3 –overlap by metal2: 1 –minimum spacing: 3 –minimum spacing to via1: 2

14. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Tub tie 4 1

15. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Spacing n diffusion/diffusion: 3 n poly/poly: 2 n poly/diffusion: 1 n via/via: 2 n metal1/metal1: 3 n metal2/metal2: 4 n metal3/metal3: 4

16. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Overglass n Cut in passivation layer. Minimum bonding pad: 100  m. n Pad overlap of glass opening: 6 n Minimum pad spacing to unrelated metal2 or metal3: 30 n Minimum pad spacing to unrelated metal1, poly, active: 15

17. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Stick diagrams n A stick diagram is a cartoon of a layout. n Does show all components/vias (except possibly tub ties), relative placement. n Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

18. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Stick layers metal 3 metal 2 metal 1 poly ndiff pdiff

19. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Dynamic latch stick diagram VDD in VSS phi phi’ out

20. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Sticks design of multiplexer n Start with NAND gate:

21. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR NAND sticks VDD a VSS out b

22. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR One-bit mux sticks VDD VSS N1 (NAND) select’ out a b N1 (NAND) out a b N1 (NAND) out a b select aiai bibi Out =((a i &s)’ &(b i &s’)’)’

23. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR 3-bit mux sticks m2(one-bit-mux) select’selectVDD VSS oioi aiai bibi m2(one-bit-mux) select’selectVDD VSS oioi aiai bibi m2(one-bit-mux) select’selectVDD VSS oioi aiai bibi select’ select a2a2 b2b2 a1a1 b1b1 a0a0 b0b0 o2o2 o1o1 o0o0

24. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Layout design and analysis tools n Layout editors are interactive tools. n Design rule checkers are generally batch--- identify DRC errors on the layout. n Circuit extractors extract the netlist from the layout. n Connectivity verification systems (CVS) compare extracted and original netlists.

25. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Automatic layout n Cell generators (macrocell generators) create optimized layouts for ALUs, etc. n Standard cell/sea-of-gates layout creates layout from predesigned cells + custom routing. –Sea-of-gates allows routing over the cell.

26. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Standard cell layout routing area

27. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Homework Set 2 Problems 2-1,2-2,2-3, 2.10 (a),(b), pp. 103-105, Textbook, Due, September 28, 2006. October -1: In problem 2.10, use the side-wall capacitance as an estimate for the overhang capacitance for a 0.5micron process. Side-wall parasitic capacitance per micrometer is specified for both p and n type diffusion on page 85. The perimeter of the channel is given by 2(W+L). The bottom-wall parasitic capacitances for p and n type diffusions are also specified on page 85. Use the area (WL) to find the total bottom-wall capacitance of the source/drain region. The total capacity is found by adding the two together.

28. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Homework Set 2 October -2: The sidewall capacitance accounts for the reverse-biased pn junctions between the source (or drain) and the substrate, and source (or drain) and the channel. Since the thickness of the source or drain diffusion is much smaller than its length or width, the perimeter of the diffusion is used to compute the sidewall capacitance. (For additional discussion, please refer to p. 110, J. M. Rabaey, Digital Integrated Circuits.) substrateW L G S D