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The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 3: Layout.

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Presentation on theme: "The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 3: Layout."— Presentation transcript:

1 The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 3: Layout of a Buffer Jason Woytowich Ritu Bajpai September 22, 2005

2 Layout Using L-Edit Create a module of a buffer, using SCMOS inverters Don’t forget to make a symbol for it

3 Layout Using L-Edit Instance your buffer into a new module and add pads to the inputs and outputs. I called it Buffer_wPads

4 Layout Using L-Edit Export your design as a tpr file.

5 Layout Using L-Edit Open L-Edit Replace Setup: C:\TannerLib\SCMOS\mhp_n05d.tpr

6 Layout Using L-Edit Go to SPR->Setup Fill in the paths for the tech library and your netlist

7 Layout Using L-Edit Go to SPR->Place and Route, Hit Run

8 Layout Using L-Edit If it completes correctly you will see this:

9 Layout Using L-Edit

10

11 Cross sections Process Definition File is C:\Program Files\Tanner EDA\L-Edit 11.0\samples\tech\mosis\mhp_n05.xst

12 Layout Using L-Edit

13 Simulating Your Layout Once the we have a layout we can simulate our design with parasitic capacitances. First draw ports over each of the pad with Metal3 selected. Give them descriptive names

14 Adding the ports

15

16 Simulating Your Layout Copy the file C:\TannerLib\tech\mosis\mhp_n05.ext into your working directory Make the following modification # Linear capacitor using Cap-Well # device = CAP( # RLAYER=cap using Cap-Well; # Plus=poly wire; # Minus=ndiff; # MODEL=; # )

17 Simulating Your Layout Go to Tools->Extract

18 Simulating Your Layout

19 Open the output in T-Spice Add simulation commands and power supplies Replace signal names where necessary.include "C:\Program Files\Tanner EDA\T-Spice 9.1\models\ml2_125.md".tran/powerup 2n 400n method=bdf.print tran v(Pad_Input,Ext_Gnd) v(Pad_Output,Ext_Gnd) V1 Ext_Vdd Ext_Gnd 5.0 V2 Pad_Input Ext_Gnd PULSE (5V 0V 0 1n 1n 50n 100n)

20 Homework Implement the following functions as a single module using only NAND gates from the SCMOS library. Test and layout. Extra points for optimal designs X = ((!A)B + A(!B)C)

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