1. ECNG1014 Digital Electronics
Sequential Logic: FSMs

2. Synchronous Sequential Networks
The block diagram of figure 4 can be modified to represent a synchronous network by replacing all the memory elements by Flip-flops which are controlled by the same clock signal (figure 6).
Figure 6: Synchronous sequential network

3. All flip-lop changes are assumed to be synchronized by a single clocking signal and change their state following the same edge of the clock. Activity in the network is cyclic with the clock signal. That activity consists of the following.
1.        Following the synchronizing clock edge:
(a)     primary input variables W1, W2…….Wn may change value,
(b)     flip-flop output variables y1, y2, ……yn may change value.

4. But all the changes must take place within a finite, know interval Tf, usually Tf is the maximum of the flip-flop propagation delays.
2. Then the new input symbol to the combinational logic, the (n +p)-tuple (W1, W2….Wn, y1, y2…..yp), propagates through that logic to form the m output Z1, Z2, …..Zm and the flip-flop input signals. All these changes must take place within a finite interval, known as interval Tg. Tg is the maximum propagation delay through the combinational logic block.

5. 3.        Then all the flip-flop input signals must be held at their final values for an interval equal to or greater than the setup time Tsu for the flip-flops. Only after this interval it is safe to another synchronizing edge to occur. The clock period T must therefore satisfy T > Tf + Tg + Tsu for reliable behaviour in the network.

6. State Model
Figure 7: State Model

7. A synchronous sequential network can be represented in two different ways (Moore and Mealy)

8. State-machine structure (Mealy)
output depends on state and input
typically edge-triggered D flip-flops

9. State-machine structure (Moore)
output depends on state only
typically edge-triggered D flip-flops

10. State-machine structure (pipelined)
Often used in PLD-based state machines.
Outputs taken directly from flip-flops, valid sooner after clock edge.
But the “output logic” must determine output value one clock tick sooner (“pipelined”).

11. State Diagram
A state diagram is a directed graph used to represent the transition and output function in a sequential system. Each state is represented by a node and each transition by an arc.
An arc from node Sk to node Sj and labelled x/z specifies that, for a present state Sk and an input x, the next state is Sj and the output is z (figure 9).

12. Figure 9: State Diagram (Mealy)Sk Sj
x/z
Figure 9: State Diagram (Mealy) x
Sj/zj
Sk/zk
State
Figure 10: State diagram (equivalent Moore)

13. A finite state machine can be represented using a state diagram or a state table. Figure 11 shows different modes of representation of a Mealy Machine
1/1
0/1 S0 S1 S2
0/0p
1/0
0/0
1/1
a) State diagram

14. b) State stable Current State S(t) Input x(t) 0 1 S0 S1,1 S2,1 S1 S0
S1, S2,1 S1
S1, S0,1 S2
S1, S2,1
S(t+1),z(t)
b) State stable

15. Present Sate
A B
Input x
Next State
NA NB
Output z
0: S0
1: S1 1
0: S2
b) State transition table
Figure 12: Different modes of representations of a finite state machine

16. State-machine analysis steps
Assumption: Starting point is a logic diagram.
1. Determine next-state function F and output function G.
2a. Construct state table
For each state/input combination, determine the excitation value.
Using the characteristic equation, determine the corresponding next-state values (trivial with D f-f’s).
2b. Construct output table
For each state/input combination, determine the output value. (Can be combined with state table.)
3. (Optional) Draw state diagram

17. Example state machine

18. Excitation equations

19. Transition equations Excitation equations Characteristic equations
Substitute excitation equations into characteristic equations

20. Transition and state tables
(transition equations)
(output equation)
transition table
state table
state/output table
another name for this function?

21. State diagram Circles for states
Arrows for transitions (note output info)

22. Modified state machine
MAXS
MAXS = Q0  Q1
Moore machine

23. Updated state/output table, state diagram

24. Timing diagram for state machine
Not a complete description of machine behavior

25. c) Specification of different types of sequential systems.
We will present two examples of specification of sequential systems. Additional systems are described in subsequent chapters.
Modulo-p Counter: A modulo-p counter is a sequential system whose input is a binary variable and whose output has integer values from the set {0,1, 2, ……,p-1}. Its time behaviour is described as follows:

26. A state description requires p states
A state description requires p states. Assigning the integers 0 to p-1 as the state labels, the following description is obtained:
Input: x(t) {0,1}
Output: z(t) {0,1, 2,……,p-1}
State: s(t) {0,1, 2,……,p-1}
Initial state: s(0) = 0
Function: the transition and output functions are: s(t+1) = [s(t) + x(t)] mod p and z(t) = s(t)
Figure 13 shows the state diagram of a modulo-5 counter.

27. Figure 13. State diagram of a modulo-5 counter.
Pattern Recognizer: A pattern recognizer is a sequential system whose binary output at time t indicates whether the input subsequence ending at time t corresponds to the particular pattern recognized by the system. Consequently, a pattern recognizer is a finite memory system – A sequential system has finite memory of length m if its output z(t) depends only on the last input values, that is z(t) = F(x(t-m+1,t)).

28. A sequential system that recognizes the pattern P = (p0,p1,…
A sequential system that recognizes the pattern P = (p0,p1,….,pm-1) has the following description:
Input: x(t) I
Output: z(t) {0,1}
Function :

29. Algorithmic State Machine (ASM)
Why State diagrams are not Enough ?
Not flexible enough for describing very complex finite state machines
Not suitable for gradual refinement of finite state machine
Do not obviously describe an algorithm: that is, well specifiedsequence of actions based on input data:
algorithm = sequencing + data manipulation
separation of control and data
Gradual shift towards program-like representation:
Algorithm State Machine (ASM) Notation
Hardware Description Languages (e.g., ABEL, VHDL or Verilog)

35. Figure 14: a) State machine; b) its equivalent ASM diagram

36. FSMs and ASMs Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Symbolic State Transition Table
State
Diagram
Encoded State Transition Table

37. Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
D FF Implementation
T FF Implementation
Timing Behavior: Input

38. FSMs/ASMs (Moore and Mealy) of the odd Parity Detector
FSM Diagrams S0 00 S0 IN IN S1 01 S1 1 IN IN S2 10
H.OUT
H.OUT
ASM Diagrams IN

39. Concept of the Synchronous Sequential Circuit
Timing: When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
• Clocking event causes state/outputs to transition, based on inputs
• For set-up/hold time considerations:
Inputs should be stable before clocking event
• After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately
Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately
sync. counter clear: effective at next clock event

40. Example: Positive Edge Triggered Synchronous System
On rising edge, inputs sampled; outputs, next state computed
After propagation delay, outputs and next state are stable
Immediate Outputs:
affect datapath immediately
could cause inputs from datapath to change
Delayed Outputs:
take effect on next clock edge
propagation delays must exceed hold times

41. Example: Vending Machine SSC
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram
Vending
Machine
SSC N D
Reset
Clk
Open
Coin
Sensor
Gum
Release
Mechanism

42. Vending Machine Example
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:
three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Draw state diagram:
Inputs: N, D, reset
Output: open

43. Step 3: State Minimization
reuse states
whenever
possible
Symbolic State Table

44. Step 4: State Encoding Next State D 0 1 1 0 X X 1 1 X X Present State
X X
X X
Present State Q N
Inputs
Output
Open X

45. Parity Checker Example
Step 5. Choose FFs for implementation
D FF easiest to use
Q1 Q0 00 D
D N Q1 N Q0 1 X 01 11 10
Q1 Q0 00 D
D N Q1 N Q0 1 X 01 11 10
Q1 Q0 00 D
D N Q1 N Q0 1 X 01 11 10
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates

46. Parity Checker Example
Step 5. Choosing FF for Implementation
J-K FF
Remapped encoded state transition table

47. Moore and Mealy Machines
State Diagram Equivalents
Moore
Machine
Mealy
Machine
Outputs are associated
with State
Outputs are associated
with Transitions

48. ASM Chart for Vending Machine

49. Another design example (from text: pp. 564 - 576)
Design a machine with inputs A and B and output Z that is 1 if:
A had the same value at the two previous ticks
B has been 1 since the last time the above was true

50. State assignment
There are 6,720 different state assignments of 5 states to 3 variables.
And there are even more using 4 or more variables
Here are a few “obvious” or “interesting” ones:

51. Transition/output table (decomposed assignment)
Simple textual substitution
With D flip-flops, excitation table is identical to transition table.

52. VHDL Coding: One "State" Process
                                                                                               
                                                                                                                                                                                                                                                                                                                                    
FSM_FF: process (CLK, RESET) begin     if RESET='1' then          STATE <= START  ;     elsif CLK'event and CLK='1' then         case  STATE  is                 when  START   => if  X=GO_MID  then                                  STATE <= MIDDLE  ;                              end if ;                 when  MIDDLE  => if  X=GO_STOP  then                                  STATE <= STOP  ;                              end if ;                 when  STOP    => if  X=GO_START  then                                  STATE <= START  ;                              end if ;                 when  others  =>  STATE <= START  ;             end case ;     end if ; end process FSM_FF ;
                                                                                                                                                                                                                                      

53. VHDL Coding: Two "State" Processes
                                                                                               
                                                                                                                                                                                                                                                                                                                                    
FSM_FF: process (CLK, RESET)    begin     if RESET='1' then          STATE <= START  ;     elsif CLK'event and CLK='1' then          STATE  <=  NEXT_STATE  ;     end if; end process FSM_FF ; FSM_LOGIC: process ( STATE , X) begin      NEXT_STATE <= STATE ;     case  STATE  is            when  START   => if  X=GO_MID  then                             NEXT_STATE <= MIDDLE  ;                        end if ;            when  MIDDLE  => ...            when  others  =>  NEXT_STATE <= START  ;         end case ; end process FSM_LOGIC ;
                                                                                                                                                                                                                                               

54. Finite State Machine Word Problems
Mapping English Language Description to Formal Specifications
Four Case Studies:
Finite String Pattern Recognizer
Complex Counter with Decision Making
Traffic Light Controller
Digital Combination Lock
T-bird tail-lights example
We will use state diagrams and ASM Charts

55. Develop excitation equations
Assume unused states have next-state = 000

56. Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior: X: Z: X: Z:

57. Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
The output is asserted whenever the input sequence ..010… has been observed, as long as the sequence 100 has never been seen.
Moore State Diagram
Reset signal places
FSM in S0
Outputs 1
Loops in State

58. Finite String Recognizer
Exit conditions from state S3:
if next input is 0 then have …0100 (state S6)
if next input is 1 then have …0101 (state S2)

59. Finite String Recognizer
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1

60. Finite String Recognizer
S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
Final State Diagram

61. Finite String Recognizer
Review of Process:
Write down sample inputs and outputs to understand specification
Write down sequences of states and transitions for the sequences
to be recognized
Add missing transitions; reuse states as much as possible
Verify I/O behavior of your state diagram to insure it functions
like the specification

62. Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: , 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M 1
Current State
000
001
010
110
111
101
Next State (Z2 Z1 Z0)
001
010
110
111
101

63. Complex Counter
One state for each output combination
Add appropriate arcs for the mode control

64. Traffic Light Controller
A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.

65. Traffic Light Controller
Picture of Highway/Farmroad Intersection:

66. Traffic Light Controller
Tabulation of Inputs and Outputs:
Input Signal
reset C TS TL
Output Signal
HG, HY, HR
FG, FY, FR ST
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
Tabulation of Unique States: Some light configuration imply others
State S0 S1 S2 S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)

67. Traffic Light Controller
Refinement of ASM Chart:
Start with basic sequencing and outputs:

68. Traffic Light Controller Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C · TL
C · TL
Equivalent ASM Chart Fragments

69. Traffic Light Controller
S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition

70. Traffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired
Complete ASM Chart for Traffic Light Controller

71. Traffic Light Controller
Compare with state diagram:
S0: HG
S1: HY
S2: FG
S3: FY
Advantages of ASM Charts:
Concentrates on paths and conditions for exiting a state
Exit conditions built up incrementally, later combined into
single Boolean condition for exit
Easier to understand the design as an algorithm

72. Digital Combination Lock
"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."
Problem specification is incomplete:
how do you set the internal combination?
exactly when is the ERROR light asserted?
Make reasonable assumptions:
hardwired into next state logic vs. stored in internal register
assert as soon as error is detected vs. wait until full combination
has been entered
Our design: registered combination plus error after full combination

73. Digital Combination Lock
Understanding the problem: draw a block diagram
Operator Data
Internal
Combination
Inputs:
Reset
Enter
Key-In
L0, L1, L2
Outputs:
Unlock
Error

74. Digital Combination Lock
Enumeration of states:
what sequences lead to opening the door?
error conditions on a second pass
START state plus three key COMParison states
START entered on RESET
Exit START when ENTER is pressed
Continue on if Key-In matches L0

75. Digital Combination Lock
Path to unlock:
Wait for
Enter Key press
Compare Key-IN

76. Digital Combination Lock
Now consider error paths
Should follow a similar sequence as UNLOCK path, except
asserting ERROR at the end:
COMP0 error exits to IDLE0'
COMP1 error exits to IDLE1'
COMP2 error exits to ERROR3

77. Digital Combination Lock
Equivalent State Diagram

78. T-bird tail-lights (text, pp585 – 591)

79. State diagram Inputs: LEFT, RIGHT, HAZ Outputs: Six lamps
(function of state only