1. CIS 020 Assembly Programming Chapter 12 - RR-Format Instructions & more RX-Format Instructions © John Urrutia 2012, All Rights Reserved.5/27/20121

2. Objectives Syntax & Use of RR-Format instructions Register Comparisons Binary or Fixed-point Multiplication / Division Condition Code branching © John Urrutia 2012, All Rights Reserved.25/27/2012

3. Register to Register RR instructions are the most efficient and are used for comparisons and arithmetic between general purpose registers. Most common RR instructions are of the form □ R where □ is a letter representing the function and the R represent the register or register-pair. □ can be: © John Urrutia 2012, All Rights Reserved.35/27/2012

4. Register to Register There are 57 RR instructions All RR instructions are 2 bytes long with the following syntax © John Urrutia 2012, All Rights Reserved.45/27/2012 RROp CodeR1R2 0-78-1112-15 First Halfword

5. Register to Register The Load Register instruction Copies the sending Register, Operand 2 to the receiving Register, Operand 1. © John Urrutia 2012, All Rights Reserved.55/27/2012

6. Register to Register The Add Register instruction Adds in binary format, the sending Register, Operand 2 to the receiving Register, Operand 1. © John Urrutia 2012, All Rights Reserved.65/27/2012

7. Register to Register The Subtract Register instruction Subtracts in binary format, the sending Register, Operand 2 to the receiving Register, Operand 1. © John Urrutia 2012, All Rights Reserved.75/27/2012

8. RR & RX Instructions The Comparison instructions - C & CR Compares a registers 4 bytes algebraically, either to a Register or Fullword. Register can be 0 through 15 Parameter should be on a fullword boundary. Failure to do this will slow down the instruction © John Urrutia 2012, All Rights Reserved.85/27/2012

9. RR & RX instructions The Condition Code is set after all arithmetic and comparison instructions. If numeric values are being compared the results can be tested using the following branch instructions © John Urrutia 2012, All Rights Reserved.95/27/2012

10. Binary/Fixed-point Multiplication When multiplying, the product can never exceed the number of digits being multiplied. Registers have a fixed 32 bits. When multiplying 32 bits * 32 bits the result is 64 bits and can’t be stored in a single register. For Fixed-point Multiplication the result is stored in a “Register Pair” consisting of an even numbered and sequentially odd numbered pair of Registers i.e. – R6 & R7 © John Urrutia 2012, All Rights Reserved.105/27/2012

11. Binary/Fixed-point Multiplication The M and MR instructions Multiplies the odd numbered register in the register pair of Operand 1, by either 4 consecutive bytes or by the specified register in Operand 2. The product is stored in the odd numbered register of the pair and overflow is in the even numbered register Operand 2 parameter should be on a fullword boundary. Failure to do this will slow down the instruction Incorrect reference to the even-odd paired registers will cause a specification ABEND S0C6 © John Urrutia 2012, All Rights Reserved.115/27/2012

12. Binary/Fixed-point Multiplication The M and MR instructions Operand 1, even-odd register pair. Odd numbered register contains the Multiplicand Operand 2, 4 Byte reference / fullword or Register Contains the Multiplier Product replaces value in the even-odd register pair. © John Urrutia 2012, All Rights Reserved.125/27/2012

13. Binary/Fixed-point Multiplication The M and MR instructions © John Urrutia 2012, All Rights Reserved.135/27/2012

14. Binary/Fixed-point Multiplication The M and MR instructions Square of R7 © John Urrutia 2012, All Rights Reserved.145/27/2012

15. Binary/Fixed-point Division The D and DR instructions Divides the even-odd register pair (64 bits) of Operand 1, by either 4 consecutive bytes or by the specified register in Operand 2 (32 bits). The quotient (32 bits) is stored in the odd numbered register of the pair and remainder (32 bits) is in the even numbered register Operand 2 parameter should be on a fullword boundary. Failure to do this will slow down the instruction Incorrect reference to the even-odd paired registers will cause a specification ABEND S0C6 © John Urrutia 2012, All Rights Reserved.155/27/2012

16. Binary/Fixed-point Division When dividing, quotients exceeding the 32 bit limit or dividing by zero will trigger a Divide Exception ( ABEND S0C9). The sign of the division is determined algebraically and is based on the dividend and divisor For negative Dividends ensure the correct sign by using the following: © John Urrutia 2012, All Rights Reserved.165/27/2012

17. Binary/Fixed-point Division The D and DR instructions © John Urrutia 2012, All Rights Reserved.175/27/2012

18. Binary Halfword Instructions Just like the binary fullword instructions: Add an H © John Urrutia 2012, All Rights Reserved.185/27/2012

19. Binary Halfword Instructions Registers using halfword instructions always refer to the low order 2 bytes of the register Because multiplying halfwords will never exceed fullword capacity there is no need for register pairs © John Urrutia 2012, All Rights Reserved.195/27/2012