2. Adaptive beamforming using QR in FPGA Richard Walke, Real-time System Lab Advanced Processing Centre S&E Division

3. 3 Contents 1Architecture of adaptive beamformer 2FPGA components Digital receiver QR processor – for adaptive weight calculation 3Design methodology 4Demonstration overview 5Conclusions

4. Architecture of adaptive beamformer Section 1

5. 5 Rx Beamformed signal Antenna Array Analogue receivers DRx Rx Digital receivers Adaptive Weight Calculation + W1W1 W2W2 WnWn Spatial filter Adaptive beamformer Architecture of adaptive beamformer

6. FPGA components Section 2

7. 7 Runtime configuration parameters  2 Image reject Bandwidth control Complex equaliser Image reject Bandwidth control Image reject Bandwidth control Image reject Bandwidth control Radar receiver specification Array of programmable ‘tap-processors’ Software configurable FIR FPGA Components

8. 8 Software programmable parameters include: –filter length –decimation ratio –complex/real arithmetic –number of channels –time varying filtering (inter & intra-pulse) Performance 20-30 GOPS on XC2V6000-5 –100 GOPS on Virtex2 Pro (2003) FPGA Components Software configurable FIR

9. 9 Building block for a range of adaptive algorithms –Sample matrix inversion (SMI) –Soft constraints –ESMI –STAP Pre-processorPost-processing QR decomposition RISC/DSP FPGA Beamforming weights Antenna data Constraints Weight calculation using QR FPGA Components

10. 10 QR decomposition FPGA Components r 2,2 r 2,3 x1x1 y r 1,1 u1u1 r 1,2 r 1,3 r 1,4 r 2,4 u2u2 u3u3 r 3,4 r 3,3 r 4,4 u4u4 x2x2 x3x3 x4x4 Input data Vectorise cell: 11 real floating- point operations Rotate cell: 16 real floating-point operations For SMI: Rw=u  (r,x) (r’,0) cos  = r r 2 +x 2 sin  = x r 2 +x 2  (u,y)(u’,y’) u’ y’ = u y cos  sin  -sin  cos 

11. 11 Good numerical properties. Arithmetic choices: –CORDIC: shift-add –Fixed-point: multiply-add –Floating-point: Higher dynamic range, allows algorithms with fewer operations & lower wordlength. Smallest! Highly parallel (Givens rotations) –Suits FPGA –Need to reduce parallelism for many applications! Features of QR FPGA Components

12. 12 1,11,31,21,41,5 2,2 2,42,32,5 3,33,53,4 4,44,5 1,6 2,6 3,6 4,6 5,55,6 2. Discrete mapping 67% utilisation 80% 60% 40% 20% 100% 83% 67% 50% 33% 100% 67% utilisation 1. Mixed mapping Obtaining lower-levels of parallelism FPGA Components

13. 13 Linear systolic array Novel mapping of QR FPGA Components

14. 14 FPGA implementation 16 11 16 139 14-bit FP operators @ 160MHz = 22 GFLOPSNumber of Ops 8xFP multipliers 2 x complex adder Complex multiplier FP add FP divider vectorise processor rotate processor rotate processor rotate processor rotate processor rotate processor rotate processor rotate processor FP add Complex multiplier XCV3200E-8 FPGA Components

15. 15 QR processor - main features FPGA Components 1 Boundary 3 Internal 32 23%6 GFLOPS2.24W 4 1 Boundary 12 Internal 82% 2 20.3 GFLOPS8W 6 LUTS Rams 3 FFs Mults 34 15K 16K 22% 23% 22% 23% 4 GFLOPS70WPentium TM 4 2GHz 1 1 Estimated (based on data from Richard Linderman) 2 Estimated (design too large for PC) 3 Also depends upon number of inputs 4 Obtained via Xpower 5 For XC2V6000-5 6 Extrapolated 101MHz 5 1 Boundary 9 Internal 74% 15 GFLOPS7W 6 14-bit mantissa 17-bit mantissa 14-bit mantissa 97MHz 100MHz 2 SizeUtilisation (XC2V6000)OperationsPower Mantissa wordlength Clock x50

16. Heterogeneous design methodology Section 3

17. 17 GEDAE TM Heterogeneous design methodology Graphically specify system

18. 18 GEDAE TM Heterogeneous design methodology Graphically specify system –primitive functions in ‘c’

19. 19 GEDAE TM Heterogeneous design methodology Graphically specify system –primitive functions in ‘c’ –executable specification

20. 20 GEDAE TM Heterogeneous design methodology Graphically specify system –primitive functions in ‘c’ –executable specification Auto-code generation –parallel programme constructed by GEDAE

21. 21 GEDAE TM Heterogeneous design methodology Graphically specify system –primitive functions in ‘c’ –executable specification Auto-code generation –parallel programme constructed by GEDAE Currently no support for FPGA –highly compatible model

22. 22 Core based methodology Heterogeneous design methodology Cores used for key functions –FFT, QR, FIR filter... –Build in parallelism (manually) –Parameterised Processor

23. 23 Core based methodology Heterogeneous design methodology Cores used for key functions –FFT, QR, FIR filter... –Build in parallelism (manually) –Parameterised Automatically generated system –communications inserted FPGA Processor FFT core from library

24. 24 Core based methodology Heterogeneous design methodology Cores used for key functions –FFT, QR, FIR filter... –Build in parallelism (manually) –Parameterised Automatically generated system –communications inserted Architectural exploration –Compaan gives Matlab NLP to VHDL –RTL output in future version FPGA Processor FFT core from library

25. Adaptive beamformer demonstration overview Section 4

26. 26 System mapping Demonstration overview Delay Sample PCI IF Virtual channel IF Chan 0 Chan 1 FPGA (TransTech PMC) Chan 2 Chan 3 QR DRx Virtual Channel API PowerPC (DNA VQG4 VME) Back- substitution Host PC (laptop) Environment synthesis and system configuration Host PC (laptop) Verification and display

27. 27 Conclusion FPGAs –Performance dependent upon level of optimisation –Floating-point is realistic –10x compute improvement –5 - 20x power improvement Design is main issue –Hardware design: High levels of parallelism required –Core-based design approaches offer interim solution –Architectural synthesis tools are emerging

28. 28 Acknowledgements The project to develop a core-based design methodology is a collaboration between: –QinetiQ Ltd poc: rlwalke@qinetiq.com –BAE SYSTEMS ATC, Gt Baddow poc: ian.alston@baesystems.com Contributions have been made by John McAllister under contract with the Queen’s University of Belfast. This work was sponsored by the United Kingdom Ministry of Defence Corporate Research Programme.