1. © 2003 Xilinx, Inc. All Rights Reserved DSP Design Flows in FPGA

2. DSP Design Flows in FPGA - 2 - 3 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only After completing this module, you will be able to: Objectives Describe the advantages and disadvantages of three different design flows Use HDL, CORE Generator, or System Generator for DSP depending on design requirements and familiarity with the tools Explain why there is a need for an integrated flow from system design to implementation Describe the System Generator and the tools it interfaces with Build a model, simulate it, generate VHDL, and go through the design flow Describe how Hardware in the Loop verification is beneficial in complex system design

3. DSP Design Flows in FPGA - 2 - 4 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

4. DSP Design Flows in FPGA - 2 - 5 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only HDL Design Verification HDL Synthesis Implementation Download HDL Implement your design using VHDL or Verilog Functional Simulation Timing Simulation In-Circuit Verification Behavioral Simulation

5. DSP Design Flows in FPGA - 2 - 6 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Synthesis Design Verification Behavioral Simulation HDL Synthesis Implementation Download HDL Synthesize the design to create an FPGA netlist Functional Simulation Timing Simulation In-Circuit Verification

6. DSP Design Flows in FPGA - 2 - 7 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Implementation Design Verification Behavioral Simulation HDL Synthesis Implementation Download HDL Translate, place and route, and generate a bitstream to download in the FPGA Functional Simulation Timing Simulation In-Circuit Verification

7. DSP Design Flows in FPGA - 2 - 8 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Labs 1-3: Generating a MAC You will be generating the MAC using three different methods –Using VHDL –Using the Xilinx CORE Generator –Using the Xilinx System Generator for DSP Compare the implementation results Contrast the design methodologies

8. DSP Design Flows in FPGA - 2 - 9 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Lab 1 Create a MAC using VHDL: Become familiar with the VHDL design flow, which includes: –Writing a small piece of VHDL code –VHDL simulation with ModelSim VHDL –Synthesizing a design using Xilinx XST –Implementation using the Xilinx ISE tools Create a 12 x 8 MAC by writing the behavioral code for a multiplier and accumulator Note: For non-VHDL users, a solution is provided in the lab1_soln directory

9. DSP Design Flows in FPGA - 2 - 10 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Block Diagram: VHDL MAC MultiplierAccumulator mult_int rdy_int 2027 12 B 8 A A CLK ND CLR Q

10. DSP Design Flows in FPGA - 2 - 11 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Wrap up Implementation results: 66 Slices, ~130 MHz Important to notice: –Global clock buffer is automatically instantiated –Embedded multiplier is used by default in Virtex™-IIP devices. In this lab, the option was turned off in order to use slice-based multipliers Timing constraint should always be used to achieve the performance required –UCF file must be generated manually Remember size to compare with the other flows

11. DSP Design Flows in FPGA - 2 - 12 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP HDL Co-Simulation Hardware Verification Resource Estimator Summary Simulink Tips and Tricks

12. DSP Design Flows in FPGA - 2 - 13 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only CORE Generator Design Verification Behavioral Simulation Synthesis Implementation Download Functional Simulation Timing Simulation In-Circuit Verification HDL COREGen Instantiate optimized IP within the HDL code

13. DSP Design Flows in FPGA - 2 - 14 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Synthesize, Implement, Download Design Verification Behavioral Simulation Synthesis Implementation Download Functional Simulation Timing Simulation In-Circuit Verification COREGen Synthesize, Implement, and Download the bitstream, similar to the original design flow HDL

14. DSP Design Flows in FPGA - 2 - 15 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only IP CENTER http://www.xilinx.com/ipcenter $P Additive White Gaussian Noise (AWGN) $P Reed Solomon $ 3GPP Turbo Code $P Viterbi Decoder P Convolution Encoder $P Interleaver/De-interleaver P LFSR P 1D DCT P 2D DCT P DA FIR P MAC P MAC-based FIR filter Fixed FFTs 16, 64, 256, 1024 points P FFT 16- to 16384- points P FFT - 32 Point P Sine Cosine Look-Up Tables $P Turbo Product Code (TPC) P Direct Digital Synthesizer P Cascaded Integrator Comb P Bit Correlator P Digital Down Converter P Asynchronous FIFO P Block Memory modules P Distributed Memory P Distributed Mem Enhance P Sync FIFO (SRL16) P Sync FIFO (Block RAM) P CAM (SRL16) P CAM (Block RAM) P Binary Decoder P Twos Complement P Shift Register RAM/FF P Gate modules P Multiplexer functions P Registers, FF & latch based P Adder/Subtractor P Accumulator P Comparator P Binary Counter P Multiplier Generator - Parallel Multiplier - Dyn Constant Coefficient Mult - Serial Sequential Multiplier - Multiplier Enhancements P Pipelined Divider P CORDIC Base Functions Memory Functions DSP Functions Math Functions Key: $ = License Fee, P = Parameterized, S = Project License Available, BOLD = Available in the Xilinx Blockset for the System Generator for DSP Xilinx IP Solutions

15. DSP Design Flows in FPGA - 2 - 16 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Xilinx CORE Generator List of available IP from or Fully Parameterizable

16. DSP Design Flows in FPGA - 2 - 17 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Relative Placement Other logic has no effect on the core Fixed Placement & Pre-defined Routing Guarantees Performance Guarantees I/O and Logic Predictability Fixed Placement I/Os Xilinx Smart-IP Technology 200 MHz Core Placement Number of Cores Device Size 200 MHz Pre-defined placement and routing enhances performance and predictability Performance is independent of:

17. DSP Design Flows in FPGA - 2 - 18 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outputs.EDN (EDIF implementation netlist).XCO (core implementation data file / log file) Optional: –.ASY Foundation or Innoveda symbols –.VEO Verilog instantiation template –.V Verilog behavioral simulation model –.VHO VHDL instantiation template –.VHD VHDL behavioral simulation model

18. DSP Design Flows in FPGA - 2 - 19 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Lab 2 Creating a MAC using Core Generator Become familiar with the CORE Generator design flow, which includes: –Generating CORE Generator macros –Instantiating the macros in VHDL –Simulating VHDL with CORE Generator macros in ModelSim –Synthesizing a design using Xilinx XST –Implementation using the Xilinx ISE 6 tools Create a 12 x 8 MAC by generating a multiply accumulator using the CORE Generator

19. DSP Design Flows in FPGA - 2 - 20 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Wrap up Implementation results: 71 slices, 175 MHz Important to notice: –Global clock buffer should be instantiated because the synthesis tool may not know which signal is the clock because it is looking at a black box

20. DSP Design Flows in FPGA - 2 - 21 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

21. DSP Design Flows in FPGA - 2 - 22 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only The Challenges for a DSP Software Platform Industry Trends –Trend towards platform chips (FPGAs, DSP) resulting in greater complexity –Highly flexible systems required to meet changing standards –Multiple design methodologies - control plane/datapath –Challenges in modeling and implementing an entire platform –Hardware in the loop verification is useful in complex system design and System Generator supports it System Design Challenges –Leveraging legacy HDL code –Modeling & implementing control logic and datapath –No expert exists for all facets of system design

22. DSP Design Flows in FPGA - 2 - 23 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only MATLAB MATLAB™, the most popular system design tool, is a programming language, interpreter, and modeling environment –Extensive libraries for math functions, signal processing, DSP, communications, and much more –Visualization: large array of functions to plot and visualize your data and system/design –Open architecture: software model based on base system and domain- specific plug-ins

23. DSP Design Flows in FPGA - 2 - 24 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only MATLAB Frequency response of input sound file

24. DSP Design Flows in FPGA - 2 - 25 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Simulink Simulink™ - Visual data flow environment for modeling and simulation of dynamical systems –Fully integrated with the MATLAB engine –Graphical block editor –Event-driven simulator –Models parallelism –Extensive library of parameterizable functions Simulink Blockset - math, sinks, sources DSP Blockset - filters, transforms, etc. Communications Blockset - modulation, DPCM, etc.

25. DSP Design Flows in FPGA - 2 - 26 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only MATLAB/Simulink Real time frequency response from a microphone: emphasizes the dynamic nature of Simulink

26. DSP Design Flows in FPGA - 2 - 27 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Traditional Simulink FPGA Flow GAP System Architect FPGA Designer Verify Equivalence HDL Synthesis Implementation Download Timing Simulation In-Circuit Verification Functional Simulation System Verification Simulink

27. DSP Design Flows in FPGA - 2 - 28 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only System Generator for DSP v6.2 – An Overview Industry’s system-level design environment (IDE) for FPGAs –Integrated design flow from Simulink to bit file –Leverages existing technologies Matlab/Simulink R13.1 or R14 from The MathWorks HDL synthesis IP Core libraries FPGA implementation tools Simulink library of arithmetic, logic operators and DSP functions (Xilinx Blockset) –Bit and cycle true to FPGA implementation Arithmetic abstraction –Arbitrary precision fixed-point, including quantization and overflow –Simulation of double precision as well as fixed point

28. DSP Design Flows in FPGA - 2 - 29 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only System Generator for DSP v6.2 – An Overview VHDL code generation for Virtex-II Pro™, Virtex™-II, Virtex™-E, Virtex™, Spartan™-3, Spartan™-IIE and Spartan™-II devices –Hardware expansion and mapping –Synthesizable VHDL with model hierarchy preserved –Mixed language support for Verilog –Automatic invocation of CORE Generator to utilize IP cores –ISE project generation to simplify the design flow –HDL testbench and test vector generation –Constraint file (.xcf), simulation ‘.do’ files generation –HDL Co-Simulation via HDL C-Simulation Verification acceleration using Hardware in the Loop

29. DSP Design Flows in FPGA - 2 - 30 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only System level modeling tool – Release 13.1 or R14 Xilinx implementation tools - ISE 6.2i Synthesis – XST & Project Navigator within ISE 6.2i – Leonardo Spectrum LS 2003b.35 – Synplify v7.2 HDL Simulation – ModelSim 5.7e Mathworks R14 Compliant!

30. DSP Design Flows in FPGA - 2 - 31 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only System Generator for DSP Platform Designs PCI/JTAG

31. DSP Design Flows in FPGA - 2 - 32 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only System Generator Based Design Flow HDL System Generator MATLAB/Simulink System Verification Synthesis Implementation Download Timing Simulation In-Circuit Verification Functional Simulation

32. DSP Design Flows in FPGA - 2 - 33 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only System Generator Based Design Flow HDL System Generator MATLAB/Simulink System Verification Synthesis Implementation Download Timing Simulation In-Circuit Verification Functional Simulation HDL-CoSimulation Files Used Configuration file VHDL IP Constraints File

33. DSP Design Flows in FPGA - 2 - 34 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only System Generator Based Design Flow HDL System Generator MATLAB/Simulink System Verification Files Used Configuration file VHDL IP Constraints File Synthesis Implementation Download Timing Simulation In-Circuit Verification Functional Simulation HWIL-CoSimulation

34. DSP Design Flows in FPGA - 2 - 35 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Creating a System Generator Design Invoke Simulink library browser To open the Simulink library browser, click the Simulink library browser button or type “Simulink” in MATLAB console The library browser contains all the blocks available to designers Start a new design by clicking the new sheet button

35. DSP Design Flows in FPGA - 2 - 36 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Creating a System Generator Design Build the design by dragging and dropping blocks from the Xilinx blockset onto your new sheet. Design Entry is similar to a schematic editor Connect up blocks by pulling the arrows on the sides of each block

36. DSP Design Flows in FPGA - 2 - 37 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Finding Blocks Use the Find feature to search ALL Simulink libraries Xilinx blockset has nine major sections –Basic elements Counters, delays –Communication Error correction blocks –Control Logic MCode, Black Box –Data Types Convert, Slice –DSP FDATool, FFT, FIR –Index All Xilinx blocks – quick way to view all blocks –Math Multiply, accumulate, inverter –Memory Dual Port RAM, Single Port RAM –Tools ModelSim, Resource Estimator

37. DSP Design Flows in FPGA - 2 - 38 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Configure Your Blocks Double-click or go to Block Parameters to view a block’s configurable parameters –Arithmetic Type: Unsigned or twos complement –Implement with Xilinx Smart-IP Core (if possible)/ Generate Core –Latency: Specify the delay through the block –Overflow and Quantization: Users can saturate or wrap overflow. Truncate or Round Quantization –Override with Doubles: Simulation only –Precision: Full or the user can define the number of bits and where the decimal point is for the block –Sample Period: Can be inherent with a “-1” or must be an integer value Note: While all parameters can be simulated, not all are realizable

38. DSP Design Flows in FPGA - 2 - 39 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Values Can Be Equations You can also enter equations in the block parameters, which can aid calculation and your own understanding of the model parameters The equations are calculated at the beginning of a simulation Useful MATLAB operators –+ add –- subtract –* multiply –/ divide –^ power –  pi (3.1415926535897.…) –exp(x) exponential (ex)

39. DSP Design Flows in FPGA - 2 - 40 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Important Concept 1: The Numbers Game Simulink uses a “double” to represent numbers in a simulation. A double is a “64-bit twos complement floating point number” –Because the binary point can move, a double can represent any number between +/- 9.223 x 10 18 with a resolution of 1.08 x 10 -19 …a wide desirable range, but not efficient or realistic for FPGAs Xilinx Blockset uses n-bit fixed point number (twos complement optional) Design Hint: Always try to maximize the dynamic range of design by using only the required number of bits 1 -2 2 0 2121 1 2020 1 2 -1 0 2 -2 1 2 -3 1 2 -4 1 2 -5 1 2 -6 0 2 -7 1 2 -8 0 2 -9 0 2 -10 1 2 -11 0 2 -12 1 2 -13 IntegerFraction Value = -2.261108… Format = Fix_16_13 ( Sign: Fix = Signed Value UFix = Unsigned value) Format = Sign _ Width _ Decimal point from the LSB Thus, a conversion is required when communicating with Xilinx blocks with Simulink blocks (Xilinx blockset  MATLAB I/O  Gateway In/Out)

40. DSP Design Flows in FPGA - 2 - 41 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only What About All Those Other Bits? The Gateway In and Out blocks support parameters to control the conversion from double precision to N - bit fixed point precision.. DOUBLE 1 -2 2 0 2121 1 2020 1 2 -1 0 2 -2 1 2 -3 1 2 -4 1 2 -5 1 2 -6 0 2 -7 1 2 -8 0 2 -9 FIX_12_9 1 2 0 2121 1 2020 1 2 -1 0 2 -2 1 2 -3 1 2 -4 1 2 -5 1 2 -6 0 2 -7 1 2 -8 0 2 -9 0 2 -10 1 2 -11 0 2 -12 1 2 -13 1111.. 2323 2424 2525 -2 6 QUANTIZATION OVERFLOW - Truncate - Round - Wrap - Saturate - Flag Error

41. DSP Design Flows in FPGA - 2 - 42 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Other Type: Boolean The Xilinx Blockset also uses the type Boolean for control ports like CE and RESET The Boolean type is a variant on the 1-bit unsigned number in that it will always be defined (High or Low). A 1-bit unsigned number can become invalid; a Boolean type cannot

42. DSP Design Flows in FPGA - 2 - 43 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Fractional Number Formats Define the format of the following twos complement binary fraction and calculate the value it represents What format should be used to represent a signal that has: Fill in the table: Using the technique shown, convert the following fractional values… 110001101011 Format = Value = Format = a) Max value: +1 Min value: -1 Quantized to 12 bit data b) Max value: 0.8 Min value: 0.2 Quantized to 10 bit data c) Max value: 278 Min value: -138 Quantized to 11 bit data

43. DSP Design Flows in FPGA - 2 - 44 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Creating a System Generator Design SysGen blocks realizable in Hardware I/O blocks used as interface between the Xilinx Blockset and other Simulink blocks Simulink sinks and library functions Simulink sources

44. DSP Design Flows in FPGA - 2 - 45 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Important Concept 2: Sample Period Every SysGen signal must be “sampled”; transitions occur at equidistant discrete points in time called sample times Each block in a Simulink design has a “Sample Period” and it corresponds to how often that block’s function is calculated and the results outputted This sample period must be set explicitly for: Gateway in Blocks w/o inputs (note: constants are idiosyncratic) Sample period can be “derived” from input sample times for other blocks

45. DSP Design Flows in FPGA - 2 - 46 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Important Concept 2: Sample Period The units of the sample period can be thought of as arbitrary, BUT a lot of Simulink source blocks do have an essence of time –For example, a sample period of 1/44100 means the block’s function will be executed every 1/44100 of a sec Remember Nyquist Theorem (Fs  2f max ) when setting sample periods The sample period of a block DIRECTLY relates to how that block will be clocked in the actual hardware. More on this later

46. DSP Design Flows in FPGA - 2 - 47 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only The Simulink System Period MUST be set in the System Generator token. For single rate systems it will be the same as the Sample Periods set in the design. More on Multi Rate designs later Setting the Global Sample Period Sample Period = 1

47. DSP Design Flows in FPGA - 2 - 48 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only SysGen Token Master Controls Slave Controls “Simulink System Period” MUST be set correctly for simulation to work

48. DSP Design Flows in FPGA - 2 - 49 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Using the Scope Click Properties to change the number of axes displayed and the time range value (X-axis) Use the Data History tab to control how many values are stored and displayed on the scope –Also can direct output to workspace Click Autoscale to quickly let the tools configure the display to the correct axis values Right-click on the Y-axis to set its value

49. DSP Design Flows in FPGA - 2 - 50 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Design and Simulate in Simulink Push “play” to simulate the design. Go to “Simulation Parameters” under the “Simulation” menu to control the length of simulations

50. DSP Design Flows in FPGA - 2 - 51 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Generate the VHDL Code Select the target device Select to generate the testbench Set the System clock period desired Generate the VHDL Once complete, double-click the System Generator token

51. DSP Design Flows in FPGA - 2 - 52 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only System Generator Output Files Design files –.VHD : VHDL design files –.EDN : Core implementation file –.XCF : Xilinx constraints file for timing constraints Project files –.NPL : Project Navigator project file –.TCL : Scripts for Synplify and Leonardo project creation Simulation files –.DO : Simulation scripts for MTI –.DAT : Data files containing the test vectors from System Generator –.VHD : Simulation testbench

52. DSP Design Flows in FPGA - 2 - 53 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

53. DSP Design Flows in FPGA - 2 - 54 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only HDL Co-simulation Allows Import of HDL Code Being able to include new or legacy modules is essential for many DSP system designers HDL modules can be imported into Simulink –“Black box” function allows designers to import HDL –Single HDL simulator for multiple black boxes –HDL modules can be simulated in Simulink to significantly reduce development time HDL is co-simulated transparently –HDL simulated using industry-standard ModelSim tool from Mentor Graphics directly from Simulink framework

54. DSP Design Flows in FPGA - 2 - 55 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Import HDL code Drag a Black Box into the model Configuration Wizard detects VHDL files & customizes block

55. DSP Design Flows in FPGA - 2 - 56 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Co-Simulate with ModelSim Drag a ModelSim block into the model Select ModelSim Simulation Mode Simulink opens ModelSim and co-simulates

56. DSP Design Flows in FPGA - 2 - 57 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

57. DSP Design Flows in FPGA - 2 - 58 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Hardware-in-the-Loop Reduces Design Time & Cost Configure any development board for hardware-in-the-loop using JTAG header in <20 minutes –Automatically create FPGA bit-stream from Simulink –Transparent use of FPGA implementation tools –Accelerate and verify the Simulink design using FPGA hardware –Mirrors traditional DSP processor design flows Combine with black box to simulate HDL & EDIF

58. DSP Design Flows in FPGA - 2 - 59 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Create Bit-stream Step 2 Generate Bit-stream Step 1 Select Target H/W Platform Step 1 Select Target H/W Platform

59. DSP Design Flows in FPGA - 2 - 60 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Co-Simulate in Hardware Step 3 contd. Post-generation script creates a new library containing a parameterized run-time co- simulation block. Step 3 contd. Post-generation script creates a new library containing a parameterized run-time co- simulation block. Step 4 Copy the a co- simulation run- time block into the original model. Step 4 Copy the a co- simulation run- time block into the original model. Step 5 Simulate for verification Step 5 Simulate for verification

60. DSP Design Flows in FPGA - 2 - 61 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Hardware in the Loop Performance Results Application Software Simulation Time (seconds) Hardware Simulation Time (seconds) Speed-up 5 x 5 Image Filter Cordic Arc Tangent Additive White Gaussian Noise Channel 1704 43X 18727 7X 60080 7.5X QAM Demodulator + Extension 120318 67X A free running clock is provided to the design, thus the hardware is no longer running in lockstep with the software. The test is started, and after some time a 'done' flag is set to read the results from the FPGA and display them in Simulink. Using this hardware co-simulation method, designers can achieve up to 6 orders of magnitude performance enhancement over original software simulation. Free Running Clock Mode Single Step Clock Mode (bit and cycle accurate) Image Filtering 6766 112X

61. DSP Design Flows in FPGA - 2 - 62 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Hardware-in-the-loop development platforms: –Xilinx XtremeDSP Development kit Multimedia Board –Distributors: Avnet, Insight, Nu Horizons –Key board vendors Alphadata, Annapolis, Nallatech, Lyrtech… –You? Configure your JTAG-based board in 20 minutes Choice of Target Hardware

62. DSP Design Flows in FPGA - 2 - 63 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

63. DSP Design Flows in FPGA - 2 - 64 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only In-System Debug at Near System Speeds Insert Chipscope block into Simulink design Configure FPGA using JTAG interface Perform in-system debug at near system speeds

64. DSP Design Flows in FPGA - 2 - 65 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

65. DSP Design Flows in FPGA - 2 - 66 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Resource Estimator The block provides fast estimates of FPGA resources required to implement the subsystem Most of the blocks in the System Generator Blockset carries the resources information –LUTs –FFs –BRAM –Embedded multipliers –3-state buffers –I/Os

66. DSP Design Flows in FPGA - 2 - 67 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Resource Estimator Three types of estimation –Estimate Area This option computes resources for the current level and all sub-levels –Quick Sum Uses the resources stored in block directly and sum them up (no sub-levels functions are invoked) –Post-Map Area Opens up a file browser and let user select map report file. The design should have been generated and gone through synthesis, translate, and mapping phases.

67. DSP Design Flows in FPGA - 2 - 68 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Lab 3 Build a MAC with System Generator: Goals: Gain familiarity with the SysGen v6.1 and its design flow, including ProjNav, synthesis tools (XST), ModelSim simulators, and the ISE implementation tools. Use Resource Estimator to estimate resources used by the design. Familiarize with hardware in the Loop flow Background: The multiply-accumulate (MAC) operation is fundamental in digital signal processing and numerous other applications For example, the output of a digital filter with impulse response h i and input sequence x i, is given by: + a b c y n =  x n-i h i i=0 N-1 c =  a i b i i

68. DSP Design Flows in FPGA - 2 - 69 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

69. DSP Design Flows in FPGA - 2 - 70 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Summary Full VHDL/Verilog (RTL code) –Advantages: Portability Complete control of the design implementation and tradeoffs Easier to debug and understand a code that you own –Disadvantages: Can be time-consuming Don’t always have control over the Synthesis tool Need to be familiar with the algorithm and how to write it Must be conversant with the synthesis tools to obtain optimized design

70. DSP Design Flows in FPGA - 2 - 71 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Summary Full VHDL/Verilog (Instantiating Primitives) –Advantages: Full access to all architecture features Carry on further with optimization Best optimization –Disadvantages: Not as portable as RTL VHDL/Verilog Must be an FPGA expert and know the architecture Time-consuming

71. DSP Design Flows in FPGA - 2 - 72 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Summary CORE Generator –Advantages Can quickly access and generate existing functions No need to reinvent the wheel and re-design a block if it meets specifications IP is optimized for the specified architecture –Disadvantages IP doesn’t always do exactly what you are looking for Need to understand signals and parameters and match them to your specification Dealing with black box and have little information on how the function is implemented

72. DSP Design Flows in FPGA - 2 - 73 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Summary System Generator for DSP –Advantages Huge productivity gains through high-level modeling Ability to simulate the complete designs at a system level Very attractive for FPGA novices Excellent capabilities for designing complex testbenches HDL Testbench, test vector and golden data written automatically Hardware in the loop simulation improves productivity and provides quick verification of the system functioning correctly or not –Disadvantages Minor cost of abstraction: doesn’t always give the best result from an area usage point of view Customer may not be familiar with Simulink Not well suited to multiple clock designs No bi-directional bus supported

73. DSP Design Flows in FPGA - 2 - 74 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

74. DSP Design Flows in FPGA - 2 - 75 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Simulink Tips and Tricks Throughout this course, we will disperse various tips and tricks that we find useful when using Simulink to create System Generator designs

75. DSP Design Flows in FPGA - 2 - 76 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Complete Systems Throughout this course, we will build and study small sections of complete systems To get a flavor of the capability of System Generator, check out the demos Type “demos” from the MATLAB command line to view them

76. DSP Design Flows in FPGA - 2 - 77 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Combining Signals To be viewed on a scope, multiple signals must first be combined Use the MUX block (Simulink library  Signals & Systems) to combine signals, thus making a vector out of them Check Format  Signal Dimensions and Format  Wide NonScalar Lines to view how many signals are combined Similarly, the DEMUX can be used to separate signals Type ‘vector’ to view the example

77. DSP Design Flows in FPGA - 2 - 78 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Creating Subsystems All large designs will utilize hierarchy Select the blocks to go into the subsystem. Click and drag to highlight a design region Select “Create Subsystem” in the Edit Menu –Ctrl+G has the same effect Use the modelbrowser under the “View” menu to navigate the hierarchy Hierarchy in the VHDL code generated is determined by subsystems

78. DSP Design Flows in FPGA - 2 - 79 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Documenting a Design Double-click the background to create a textbox Type in the text Right-click the text to change format Left-click to move the textbox around A masked subsystem can be given “Help” documentation. More on this later

79. DSP Design Flows in FPGA - 2 - 80 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Inports and Outports Allow the transfer of signal values between a subsystem and a parent Inport and Outport block names are reflected on the subsystem Can be found in Simulink  Sinks (for the Outport) and Simulink  Sources (for the Inport)

80. DSP Design Flows in FPGA - 2 - 81 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Inputting Data from the Workspace “From Workspace” block can be used to input MATLAB data to a Simulink model Format: –t = 0:time_step:final_time; –x = func(t); –make these into a matrix for Simulink Example: –In the MATLAB console, type: t = 0:0.01:1; x = sin(2*pi*t); simin = [t', x']; Type ‘FromWorkspace’ to view the example

81. DSP Design Flows in FPGA - 2 - 82 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outputting Data to the Workspace “To Workspace” block can be used to output a signal to the MATLAB workspace The output is written to the workspace when the simulation has finished or is paused Data can be saved as a structure (including time) or as an array Type ‘ToWorkspace’ to view the example