1. J.L. BIARROTTE, S. BOUSSON, C.JOLY, T. JUNQUERA, J. LESREL, L.LUKOVAC Institut de Physique Nucléaire (CNRS/IN2P3) 91406 Orsay – France O. LE DORTZ, J-F GENAT, H. LEBBOLO, D. MARTIN LPNHE PARIS (CNRS/IN2P3) France Abstract: Within the framework of the current European research programs EUROTRANS and EURISOL on High Intensity Proton Accelerators, and particularly on the R&D on superconducting SPOKE cavities, a Low Level Radio Frequency Digital system is developed at IPN Orsay in collaboration with LPNHE Paris, both IN2P3-CNRS laboratories. Due to Lorentz's forces, mechanical vibrations or RF power perturbations, the amplitude and phase of the electromagnetic wave inside the cavities need to be controlled. Other goals are a better reliability, a high level of integration and a fast response time of the feedback control system. Digital techniques should allow to meet all of these goals and provide an improved flexibility compared to analog techniques, with the integration of the main algorithms and functions into an FPGA. The main design options and some preliminary results are presented. LPNHE PARIS Stability of the amplitude :0.1% Stability of the phase of the accelerating field : 0.5° Response time : less than 10 µs Reliability close to 100% implying a strong integration and an efficient monitoring and control software TECHNICAL TRENDS TECHNICAL TRENDS Use of standard instrumentation Hardware structure Development of Cavity IQ and PID models Integration Use of ADC, DAC, and digital processors I/Q modulator AMPLI Down converter system ADC IQ Demodulation Control and Monitoring PID DAC I/Q modulator Communication block Feed forward FPGA Main loop MATLAB SIMULINK PXI crate using a PCI bus link for the monitoring and control of the FPGA’s algorithms parameters ALTERA STRATIX FPGA with internal fast blocks PXI card SIMULATIONS 14 bits ADC and DAC Tr ~ 5µs with PI IQ Demodulation with 8 interleaved samples VHDL simulation of the PXI card PXI CARD x 8 Clock 80MHz multiplier Band pass filter IF=10MHz Ref 352.2MHz Ref 10MHz RF generator Hybrid coupler 90° Hybrid coupler 90° Combiner RF1 IF1 RF2 IF2 OL1 OL2 Image reject mixer G GG G G Amplification and matching AA AAA A G 342.2MHz DOWN CONVERTER SYSTEM GOALS INCI_In TRAN_In REFL_In REFC_In 14 bit ADC AD6645 14 bit ADC AD6645 14 bit ADC AD6645 AD 8138 cPci Interface Cyclone EP1C4 BGA324 Compact PCI / PXI PROM EPCS1 Vregs 3.3 et 5V -12V 3.3 et 1.5V (FPGA) +5 et -5V (Analog) IQ Detection Stratix EP1S20 BGA484 Active Serial Config Config FPP JTAG PCK111 Clock driver 80 MHz Clk 14 bit ADC AD6645 14 Add, Dat, R/W AD 8138 x4 DAC AD9764 DAC AD9764 14 AD8047 256k 18bits 4ns RAM CY7C1327F-133AC Clocks LVPECL PROM EPC4 33 MHz Clk 352.2 MHz RF_Mod Dig_In 4 4 Dig_Out Modul. AD8345 14 AD8047 DAC AD9764 REFC_In INCI_In REFL_In TRAN_In Pi Pr Pt SCHEDULE Tests of the global system with a copper cavity at T°=290K Development of a second PXI card for the research program EUROTRANS :fault-tolerance Tests of the global system with a SPOKE cavity at T°=4.2K Digital processing latency: 100ns 35 x 9 bit multipliers SIMULINK modeling of the cavity and feedback loop Simulink simulation results