1. 1 C.H. Ho © Rapid Prototyping of FPGA based Floating Point DSP Systems C.H. Ho Department of Computer Science and Engineering The Chinese University of Hong Kong 30JUN2002

2. 2 C.H. Ho © Overview oIntroduction oObjective oFloat Design Flow oFloating Point Number Representation oFloat Class oOptimization oDigital Sine-Cosine Generator oResults oConclusion

3. 3 C.H. Ho © Introduction oFPGA based DSP systems prototyping methodology l Using standard programming language for simulation and verification l Using floating point arithmetic on simulation l Using fixed point operation on implementing hardware oFPGA systems could adapt Floating Point arithmetic l Less overhead in developing DSP systems l FPGA density has improved for using floating point operation oFloat – A tools for porting floating point algorithm into hardware l Simulation/Optimization/Implementation can be completed using a single description l Optimize the floating point operation to balance the quantization error and the circuit size l Translate of a high level algorithmic description to an FPGA implementation (under development)

4. 4 C.H. Ho © Objective oThe tools have the following features l Designer need not have expertise in the implementation of floating point arithmetic l The size of exponent and fraction of the floating point number can be different for each signal l The optimizer uses a user-specified set of input vectors and a cost function which takes into account the tradeoff between quantization error and the size of circuit l Reduced the design time Simulation is done in high level Hardware implementation is correct by automatic construction

5. 5 C.H. Ho © Float Design Flow oAlgorithm is described in Perl Language using the class Float oCost function suggests the circuit size and quantization error required oOptimizer will minimizes the cost function by varying the precision of Float object oSimulate the algorithm by executing the program oVHDL code produced by compiler

6. 6 C.H. Ho © Floating Point Number Representation oBased on the IEEE 754 Floating Point Number Format oe – biased exponent of – fraction oebits – size of exponent obias = 2 ebits-1 –1 oNumbers = 1.f x 2 (e-bias) oIEEE double precision is used as reference signal for computation of quantization error

7. 7 C.H. Ho © Float Class oSimulation of arbitrary precision floating point arithmetic oCore method l add()/multiply() Return a new Float object representing the sum/product of the argument Calculate the IEEE 754 double precision as a reference value for computing quantization error Store the maximum and minimum range of this value for finding minimum exponent l setExponentSize()/setFractionSize() Adjust the size of the floating point number l getValue()/setValue() Retrieve/write the value represented by Float object l getQERR() Return the quantization error between the arbitrary size floating point number and IEEE double precision reference value

8. 8 C.H. Ho © Optimization oTwo factors: Quantization Error/Circuit Size oQuantization Error (QERR), in decibels oArea of the floating point adder, in Virtex slices oArea of the floating point multiplier, in Virtex slices oCost Function (a and b are non-negative weightings):

9. 9 C.H. Ho © Optimization oUses Nelder-Mead method to minimize the cost function oDesigner can adjust a, b to weight the relative importance of area and QERR oOptimization procedure l Change the precision of Float variable l Simulation the algorithm function at the specified precision l Compare the result with the reference result and compute the cost function l Repeat until the optimization terminates

10. 10 C.H. Ho © Digital Sine-Cosine Generator oLet s1 and s2 denote the two outputs of a digital sine- cosine generator  We will use cos(  ) = 0.9 in this paper

11. 11 C.H. Ho © Digital Sine-Cosine Generator o$cos_theta = new Float(23, 8, 0.9); o$cos_theta_p1 = new Float(23, 8, 1.9); o$cos_theta_m1 = new Float(23, 8, -0.1); o$s1[0] = new Float(23, 8, 0); o$s2[0] = new Float(23, 8, 1); ofor ($i = 0 ; $i < 50 ; $i ++) { o $s1[i+1] = $s1[$i] * $cos_theta + o $s2[$i] * $cos_theta_p1; o $s2[i+1] = $s1[$i] * $cos_theta_m1 + o $s2[$i] * $cos_theta; o}

12. 12 C.H. Ho © Digital Sine-Cosine Generator oThis algorithm can be passed to different component for processing l Simulation By executing the program, the correctness of the algorithm can be verified l Optimization Determine the suitable precision format for each of the five Float objects in the algorithm function l Implementation Parsing the inner loop to produce an expression tree Generating the VHDL for implementation of reconfigurable computing platform

13. 13 C.H. Ho © Results oDifferent Configuration of Floating Point operator Implemented Fraction SizeCircuit Size (Virtex slices) Frequency (MHz)Latency (cylces) Multiplication 71781038 153751028 235981008 316941008 Addition 7120587 15225467 23336417 31455407

14. 14 C.H. Ho © Results oSimulation of Algorithm

15. 15 C.H. Ho © Results oQuantization Error

16. 16 C.H. Ho © Results oOptimization Result

17. 17 C.H. Ho © Conclusions oThe Float Environment l Enable designers to concentrate on higher level algorithmic issue l Increasing the productivity oThe digital sine-cosine generator was implemented l Using Float Environment l Simulation and Optimization involved l Achieve 2% - 5% reduction in area

18. 18 C.H. Ho © Thank You Q & A