1. Department of Communication Engineering, NCTU 1 Unit 5 Programmable Logic and Storage Devices – RAMs and FPGAs

2. Department of Communication Engineering, NCTU 2 Unit 5-1 Static Random Access Memory (SRAM)

3. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 3 Reason for using random access memory (RAM)  Computers and other digital systems perform operations that retrieve, manipulate, transform and store data  Read only memories (ROMs) can not dynamically store data  Registers support fast and random storage, but cannot be used for mass storage because they are implemented with FFs and occupy too much physical area  RAM is faster and occupies less area than a register file Most RAMs are volatile- the information vanishes after power is removed from the device There are two types of RAMs: static and dynamic  Dynamic RAMs need refresh and static RAMs don’t

4. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 4 Basic static RAM (SRAM) structure Word EN Bit_line_N Bit_line cell Cell_N Word EN Bit_line_N Bit_line

5. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 5 module SRAM1 (data_out, data_in, CS_N,WE_N); outputdata_out; inputdata_in; inputCS_N, WE_N; wire data_out = (CS_N==0) ? (WE_N==0) ? data_in : data_out : 1’bz; endmodule Level-sensitive Verilog models of RAMs A 32K  8 SRAM data_out CS WE data_in CS WE OE Mux Demux D_IN D_OUT CS WE OE Mux Demux D_IN D_OUT CS WE OE Mux Demux D_IN D_OUT CS WE OE Mux Demux D_IN D_OUT CS WE OE Mux Demux D_IN D_OUT CS WE OE Mux Demux D_IN D_OUT CS WE OE Mux Demux D_IN D_OUT CS WE OE Mux Demux D_IN D_OUT Decoder data_in data_out

6. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 6 Basic static RAM (SRAM) structure A 16K SRAM module SRAM2 (data, CS_N,WE_N,OE_N); outputdata_out; inputCS_N, WE_N,OE_N; wire latch_out = ((CS_N==0) && (WE_N==0)&&(OE_N==1)) ? data : latch_out; assign data = ((CS_N==0) && (WE_N==1)&&(OE_N==0)) ? latch_out : 1’bz; endmodule data CS OE WE Column Input/Output A 10 A 9 A 0 A3A3A2A2A1A1A0A0A3A3A2A2A1A1A0A0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

7. Department of Communication Engineering, NCTU 7 Unit 5-3 Altera FPGA Architecture

8. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 8 Architecture of Stratix  Logic array blocks (LABs) : 10 logic elements (LEs) in each LAB  Memory block structures 512 RAM: simple dual-port memory blocks (512 +parity =576) M4K RAM: true dual-port memory blocks (4K + parity =4608) M-RAM: true dual-port memory blocks (512K+parity=589,824)  DSP blocks 9×9- or 18×18- or 36×36-bit multiplier with add and subtraction 18-bit input shift registers  I/O element (IOE) : contains a bidirectional I/O buffer and six registers Supports single-ended, differential I/O standards and external memory devices such as DDR-SDRAM

9. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 9

10. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 10 Logic elements (LE) : the smallest unit of logics in the Stratix architecture each of which contains :  A four-input LUT  A programmable register : can be configured for D, T, JK and SR FFs Asynchronous data,  Support single bit addition and subtraction

11. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 11

12. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 12

13. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 13

14. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 14

15. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 15

16. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 16

17. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 17

18. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 18

19. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 19 Single-Clock SRAM without read-through-write behavior module ram_infer (q, a, d, we, clk); output reg [7:0] q; input [7:0] d; input [6:0] a; input we, clk; reg [7:0] mem [127:0]; always @ (posedge clk) begin if (we) mem[a] <= d; q <= mem[a]; // q doesn't get d in this clock cycle end endmodule clk we a A0A0 A1A1 A3A3 d d(A 0 ) + d(A 1 ) + d(A 3 ) + q d(A 1 ) d(A 0 ) A2A2 d(A 2 ) + d(A 2 )

20. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 20 Single-Clock SRAM with read-through-write behavior module ram_infer (q, a, d, we, clk); output [7:0] q; input [7:0] d; input [6:0] a; input we, clk; reg [6:0] read_add; reg [7:0] mem [127:0]; always @ (posedge clk) begin if (we) mem[a] <= d; read_add <= a; end assign q = mem[read_add]; endmodule clk we a A0A0 A1A1 A3A3 d d(A 0 ) + d(A 1 ) + d(A 3 ) + q d(A 1 ) + d(A 0 ) + A2A2 d(A 2 ) +

21. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 21

22. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 22

23. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 23

24. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 24

25. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 25

26. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 26

27. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 27

28. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 28

29. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 29

30. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 30

31. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 31

32. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 32

33. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 33

34. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 34

35. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 35

36. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 36

37. Department of Communication Engineering, NCTU 37 Unit 5-4 Model Simulation Library

38. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 38 Choose a working directory that you want to store the compiled Libraries

39. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 39 Create a new library for the compiled library

40. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 40 Create the library named: stratix_atoms Repeat the above two procedures For the following two libraries altera_mf 220model

41. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 41 Compile the stratix_atomsLibrary

42. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 42 Choose the stratix_atoms.vfile

43. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 43 Notice the difference from Map the stratix_atoms to the compiled stratix_atoms library

44. Department of Communication Engineering, NCTU 44 Unit 5-5 Simulation with Altera mega-functions

45. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 45 Load Altera_mf library

46. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 46 Load Altera_mf Then you are done

47. Department of Communication Engineering, NCTU 47 Unit 5-5 Post Layout Simulation

48. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 48 Specify options for Generating output files For modelsim File name : *.vo

49. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 49 Import top-level Test bench and top-level design *.vo only

50. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 50 Load Stratix_atoms library

51. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 51 Load Stratix_atoms library

52. Digital CASUnit 5 : SRAMs and FPGAsSau-Hsuan Wu Department of Communication Engineering, NCTU 52 Notice!! the Instance name of the top-level design, not its module name Load *.sdo file From the SDF Option and apply it to the Top-level design