1. Simply Better Synthesis ® Xilinx Distributor Training October 21

2. Synplicity Confidential LCANET,5 PROG,SYNPLIFY,3.0,"Thu Jul 17 09:40:28 1997" PART,4010xlbg256-09 SIG,CLK_c,TNM=CLK PWR,0,GND PWR,1,VCC SYM, inst2_DATA0$c1_2$$cy4, CY4, HU_SET=inst2$USET0, LIBVER=2.0.0, RLOC=R0C0 PIN, A0, I, DATA0_c PIN, A1, I, DATA0_c LCANET,5 PROG,SYNPLIFY,3.0,"Thu Jul 17 09:40:28 1997" PART,4010xlbg256-09 SIG,CLK_c,TNM=CLK PWR,0,GND PWR,1,VCC SYM, inst2_DATA0$c1_2$$cy4, CY4, HU_SET=inst2$USET0, LIBVER=2.0.0, RLOC=R0C0 PIN, A0, I, DATA0_c PIN, A1, I, DATA0_c Synplify-M1 Design Flow and Output Logic comb: process (pres_state) begin case pres_state is when S0 = z <=‘0’; next_state <= S0; else z <=‘0’; next_state <= and Output Logic comb: process (pres_state) begin case pres_state is when S0 = z <=‘0’; next_state <= S0; else z <=‘0’; next_state <= Behavioral HDL Model Technology M1 input [4:0] ReadRegSel; input WriteReg; output [15:0] RegData; ram32x16 RAM_BLOCK (.Q(RegData),.WE(WriteReg),.Clock(Clk),.Data(WriteR input [4:0] ReadRegSel; input WriteReg; output [15:0] RegData; ram32x16 RAM_BLOCK (.Q(RegData),.WE(WriteReg),.Clock(Clk),.Data(WriteR XNF Structural HDL Synplify Mapped Verilog or VHDL netlist for Post Synthesis Simulation

3. Synplify Benefits HDL Analyst –Interactive Debugger –Instant Understanding Language Sensitive Editor TCL Scripting Superior Quality of Results Direct Synthesis Technology –New/Improved Mappers Timing-Driven Synthesis FSM Compiler Incredibly Fast Runtime 2 to 120x Performance Linear Compile Times Optimal Area & Speed Ease Of Use Fast

4. Synplicity Confidential Device support in Synplify v3.0 XC3000 XC4000 XC4000E XC4000EX XC4000L XC4000XL XC5200 XC9500

5. Synplicity Confidential Easy-to-use, push-button synthesis Compiles in minutes, even for 100k gates Architecture Specific- mapping yields Highest Quality of Results Language Sensitive Editor Simply Better Synthesis Default Clock Frequency Unique FSM Compiler

6. Synplicity Confidential Graphical views have been done before, just not done well…. What Makes HDL Analyst different: RTL View is an intermediate view Hierarchy shows layers of complexity Cross-Probing gives instant understanding Find-By-Name jumps to the object HDL Analyst

7. Synplicity Confidential Describe The Functionality Understand and Analyze Graphically See The Actual Technology Mapping Cross-Probing relates the different views/concepts HDL Analyst

8. Synplicity Confidential HDL Analyst Critical Paths Shows What You Need To Improve Use Filter Schematic To Show Only The Relevant Logic

9. Synplicity Confidential Designer always sees most effective view of design - improves productivity Instant understanding of how views are related Graphically displays paths for further tuning Puts all selected instances on a single page for easy analysis Problem nets instantly identified in schematic and source HDL source, RTL schematic and technology-specific gate-level views displayed Cross-probing among all three views Critical path display Filter Schematic Find-by-name Feature Benefit HDL Analyst

10. Synplicity Confidential Design Entry Hierarchical Projects Xilinx Specific Macros Xilinx I/Os Applying Attributes Automation Through TCL

11. Synplicity Confidential Hierarchical Projects What is a black box? –Black boxes are modules where just the interface is specified, and the internals are ignored by Synplify. Black boxes can be used to directly instantiate: Vendor primitives and macros (including I/Os). –LogiBLOX User-designed macros whose functionality was defined in a schematic editor, or another input source. (When the place and route tool can merge design netlists from different sources.)

12. Synplicity Confidential Hierarchical Projects (contd) Verilog Designs –Create a stub for the macro with no contents.The stub must declare the ports and the port directions. Specify that Synplify should ignore the contents by putting the "black_box" synthesis directive just before the semicolon ';' on the module declaration. module myram(out, in, addr, we) /* synthesis black_box */ ; output [15:0] out; input [15:0] in; input [4:0] addr; input we; endmodule

13. Synplicity Confidential Hierarchical Projects (contd) VHDL Designs –Create a component declaration for the black box user macro. –Include the Synplify supplied attributes package. –Define the black_box attribute on the black box component to be true. library IEEE; use IEEE.std_logic_1164.all; use synplify.attributes.all; -- entity goes here architecture struct of top is component myram (outp: out std_logic_vector(15 downto 0); inp : in std_logic_vector(15 downto 0); addr: in std_logic_vector(4 downto 0); we: in std_logic); end component; attribute black_box of myram : component is true; -- architecture begins here

14. Synplicity Confidential How to instantiate Xilinx Macros Black Box LogiBLOX modules/architectures Verilog Designs –Predefined Xilinx Macros Manual Instantiation Predefined I/Os Black Box –To Use: Add \lib\xilinx\xc3000.v to project list Add \lib\xilinx\xc4000.v to project list Alternatively use `include

15. Synplicity Confidential How to instantiate Xilinx Macros (contd) VHDL Designs –Predefined Xilinx Macros Manual Instantiation Predefined I/Os Black Box –To Use: Add the appropriate library and use clauses library ; use.components.all; where is xc3000, xc4000.

16. Xilinx I/O Attributes Attributes –xc_nodelay (boolean attribute) Remove default input delays on flops and latches. Available for XC4000 INFF/INLAT and for XC5200 DFF and DLAT symbols. For the 5000 family this attribute must be applied on the IBUF symbol. –xc_fast (boolean attribute) Decrease the transition time on output driver. Available for XC3000/XC4000 and XC5200 family.

17. Synplicity Confidential Xilinx I/O Attributes Attributes (contd) –xc_slow (boolean attribute) Increase the transition time on the output driver. Available for the XC3000/XC4000 and XC5200 family. –xc_fast (boolean attribute) Decrease the transition time on output driver. Available for XC3000/XC4000 and XC5200 family.

18. Synplicity Confidential Xilinx I/O Attributes Attributes (contd) –xc_cmos (boolean attribute) Specifies that a CMOS pad type be used for the port. CMOS pads are slower than the TTL pads. The TTL pads are used by default in Synplify, so use this command to pick slower pads. To slow down CMOS pads further, use the xc_slow attribute on the port. –xc_ttl (boolean attribute) Specifies that a TTL pad type be used for the port. This is the default. The TTL pads are faster than the CMOS pads. To make it even faster, use the xc_fast attribute on the port.

19. Synplicity Confidential Xilinx I/O Attributes Attributes (contd) –syn_maxfan (integer attribute) Overrides the default fanout set in the Set Device Options form (or with the "set_option -fanout_limit" Tcl command) for an individual input port or register output. –syn_noclockbuf (boolean attribute) To specify use of normal input buffer rather than a clock buffer resource for the clock signal. –xc_loc (string attribute) Specifies the placement location for the port. Valid locations are defined in xilinx databook.

20. Synplicity Confidential Applying Attributes TCL –define_attributecommand define_attribute tcl command can be applied by using a constraint file (.sdc file). Example: define_attribute syn_noclockbuf 1 HDL source –Verilog meta-comment Example : module my_design(out, in, clk_in); output out; input in; input clk_in /* synthesis syn_noclockbuf = 1 */

21. Synplicity Confidential Applying Attributes (contd) –VHDL attributes library ieee; use ieee.std_logic_1164.all; use synplify.attributes.all; entity simpledff is port (q : out std_logic_vector(7 downto 0); d : in std_logic_vector(7 downto 0); clk : in std_logic); attribute syn_noclockbuf of clk : signal is true; end simpledff; architecture arch1 of simpledff is begin -- architecture goes here end acrh1;

22. Applying Attributes Verilog Example module counter4 (cout, output_vector, input_vector, ce, load, clk, rst); // remove the input delay on load input load /* synthesis xc_nodelay=1 */ ; // make output_vector transition quickly output [3:0] output_vector /* synthesis xc_fast=1 */ ; … endmodule

23. Applying Attributes VHDL Example use synplify.attributes.all; entity counter4 is port (cout: out bit; output_vector: out bit_vector (3 downto 0); input_vector: in bit_vector (3 downto 0); ce, load, clk, rst: in bit); -- remove the input delay on load attribute xc_nodelay of load: signal is true; -- make output_vector transition quickly attribute xc_fast of output_vector: signal is true; end counter4;

24. Here is an example tcl script that creates new project, adds a design to the project, sets technology specific options and runs Synplify. It also runs the rtl and gate level analyst and launches notepad to view the log file. It's that easy.... #Xilinx-XL Example TCL script shifter.tcl set_option -technology XC4000XL set_option -part XC4005XL set_option -package PC84 set_option -speed_grade -09 add_file -verilog “d:/qa/shifter.v” add_file -constraint “d:/qa/shifter.sdc” set_option -default_enum_encoding onehot set_option -symbolic_fsm_compiler true set_option -frequency 0.000 set_option -fanout_limit 100 set_option -force_gsr true set_option -disable_io_insertion false set_option -xilinx_m1 true set_option -result_file “d:/qa/shifter.xnf” project -run open-file -rtl_view open_file -technology_view project -save “d:/qa/shifter.prj” project -log_file “d:/qa/shifter.srr” open_file -edit_file “d:/qa/shifter.srr” #End TCL example TCL Script Example:

25. Synplify Benefits HDL Analyst –Interactive Debugger –Instant Understanding Language Sensitive Editor TCL Scripting Superior Quality of Results Direct Synthesis Technology –New/Improved Mappers Timing-Driven Synthesis FSM Compiler Incredibly Fast Runtime 10x to 100x Performance Linear Compile Times Optimal Area & Speed Ease Of Use Fast

26. Synthesizing Xilinx FPGA/CPLDs with Synplify

27. Quality of Results Area Delay Focus on the “sweet region” Tighter range on synthesis results Traditionally from ASIC Synthesizers

28. State Machines Synplify includes the symbolic FSM Compiler to adapt state machines to Xilinx FPGA architectures. Synplify is the only synthesis tool that automatically identifies and extracts state machines for optimization and re-encoding. –1-hot implementation –FSM Switch –reachability analysis

29. Resource Sharing Resource sharing is always done automatically unless turned off. S S A B C D C A Which is better? Circuit #1 Circuit #2 S D B

30. Technology Mapping. Typical (fine- grained) Mapping Synplify’s Direct Technology Mapping.

31. Synplify Xilinx Optimizations Outputs xnf for M1 and XACT Maps directly to FMAPs, HMAPs and carry primitives Performs Module Generation Uses: –flip-flop load enable –GSR –Clock buffer resources –Carry chain resources Automatic I/O insertion Supports user-instantiation

32. How Synplify DST works with M1 & Xilinx Architecture to give the best results Synplify employs DST (Direct Synthesis Technology) to map directly to the architecture of the targeted Xilinx part, not to gates. If hardwired carry logic is available for arithmetic functions, then Synplify uses it, for example: –Arithmetic Functions are mapped directly to RPMs using the built in carry logic, bypassing XBLOX. This allows Synplify to map logic around the arithmetic function into the unused capacity of the lookup tables used for the arithmetic function –Synplify generates RPMs differently for the M1 release to allow M1 to specify the relative location of the carry chain. This improves routability.

33. Xilinx 4000[E,EX,XL] Dedicated routing from 4- LUT to 3-LUT. Carry logic for arithmetic functions. Flip-flop load enable. Carry 4-LUT 3-LUT CIN COUT

34. Synplicity Confidential Technology-Specific Optimizations case sel is when “00” => z <= a; when “01” => z <= b; when “10” => z <= c; when “11” => z <= d; when others => z ‘x’); end case; a b sel[0] c d sel[0] z F G H Xilinx XC4000EX CLB sel[1]

35. Synplicity Confidential Module Generation Example F G carry F G clb F G carry F G clb b[3:0] a[3] a[2] a[1] a[0] cond z[3] z[2] z[1] z[0] carry F G clb carry F G clb z[3] z[2] z[1] z[0] cond b[3] a[3] a[2] b[2] cond b[1] a[1] a[0] b[0] cond If(cond) z = a+1; else z = b; The Simple Approach Context-Sensitive Module Generation

36. Asynchronous set/reset flipflops/latches Does not have the DFFRS or the LATRS –XNF netlist is provided for LD_1, LDC_1, LDP_1, LDCP_1 and DFFRSE. setreset: process (clk, reset, set) begin if reset = '1' then qrs <= '0'; elsif set = '1' then qrs <= '1'; elsif rising_edge(clk) then qrs <= data; end if; end process setreset; data clk reset set qrs

37. Synplicity Confidential CPLD Example module cntload(q,d,ld,en,clk); output [3:0] q; input [3:0] d; input ld, en, clk; reg [3:0] q; always @(posedge clk) begin if (ld) q = d; else if (en) q = q + 1; end endmodule

38. Synplicity Confidential Xilinx CPLD Specific Optimization RTL View

39. Synplicity Confidential Xilinx CPLD Specific Optimization Technology View

40. Synplicity Confidential Quality of Results Improvements Module generation for 4000/4000E/4000EX/4000XL and 5200 devices M1 option for Xilinx devices Takes advantage of new M1 place & route tools Better module generation for datapaths All New Critical Path Restructuring to improve timing Critical Path Resynthesis

41. Synplicity Confidential Timing-Driven Synthesis Make Area vs Performance Tradeoffs Clock constraints –Multiple clock paths Multi-cycle path handling

42. Synplicity Confidential Multiply delay Timing Driven Synthesis Define_reg_output_delay Define_reg_input_delay Define_output_delay Define_multicycle_path Define_clock Define_input_delay D Q D Q

43. Synplicity Confidential Timing Driven Synthesis Design Constraint –Constraints Forwarded to P&R Optimization Constraint –-improve Restructure the design during optimization to help meet timing goals Place & Route Constraint –-route Add additional routing delay in its calculations to help meet timing goals Applies to input, output, and clock constraints

44. Synplicity Confidential Timing Driven Synthesis Architecture Specific Timing (Estimated) Design Constraints P&R Attributes Optimizer Synplify Timing Report -route P&R Attributes EDIF Netlist Xilinx P&R Vendor Specific Netlist Design Constraints (Future) Timing report P&R delay compensation ( -route) Optimization directive (-improve)

45. Synplicity Confidential Constraint file example Timing constraint examples define_clock CLK -period 15.0 define_input_delay {I[7:0]} -improve 2.0 define_multicycle_path -to {alu_inst.out[0]} 2 define_output_delay q 3.0 Xilinx specific attribute constraints define_global_attribute syn_noclockbuf 1

46. Synplicity Confidential Synplify Product Status

47. Synplicity Confidential Synplify 3.0 - Released June ‘97 Introduced HDL Analyst –RTL Level Viewer –Technology Mapped View Introduced TCL Scripting and Constraints –New timing constraints (in nanoseconds and clock MHz) –Timing Reports calibrated in NS –10% to 20% better (faster) results than previous release

48. Synplify Updates TCL Licensed for All Users (3.0a) Improved syn_preserve/syn_sharing support (3.0a) Complex latch inferencing reduces feedback muxes (3.0a) Upgrade To The Latest Version

49. Synplify Futures for Xilinx Continued Optimization Improvement –10 % Area Improvement for M1 Devices 3.0b –Improved Synthesis For Multiplier 3.0b New Architecture Support Capability to pass contraints to M1 Xilinx specific placement hints to XACT/M1 for improving timing

50. Synplicity Confidential Frequently Asked Questions

51. Synplicity Confidential Frequently Asked Questions Does Synplify read XNF/EDIF? –No. Synplify is a behavioral Synthesis tool. We read in VHDL and Verilog HDL design descriptions and write out highly optimized XNF netlist for xilinx place and route. Does Synplify have schematic input or output? –Synplify does not have a schematic input. Synplify only accepts VHDL and Verilog inputs. Synplify v3.0 has the “HDL Analyst” feature where one can view RTL and technology views of the design.

52. Synplicity Confidential FAQ (contd) Does Synplify offer simulation? –No. There are a lot of simulators available for VHDL and Verilog which do the job. Does Synplify do timing analysis and timing optimization? –Yes. Synplify does timing-based optimization and shows critical paths based on cell delays and estimated route delays. Timing constraints can be supplied in the form of arrival/required times in nanoseconds and clock frequency constraints in Mhz or nanoseconds.

53. Synplicity Confidential FAQ (contd) Does Synplify support vendor primitive or macro instantiation? –Yes. For xilinx we supply an import library specific to each family. An import library is a Verilog or VHDL description of the primitives and macros as needed for synthesis. All you need to do is let Synplify know you require the import library for your design. This can be done with a “`include…” in Verilog or with a “library …” statement in VHDL.

54. Synplicity Confidential FAQ(contd) What goes in the Synplify Source file list? –All the source files in your design and the constraint file (if any). In Verilog, do not include files that are referenced from a `include statement. For VHDL, one must include files that contains user defined packages. You do not need to include the files for the IEEE libraries, or any vendor import libraries that Synplify supports.

55. Synplicity Confidential FAQ(contd) How does Synplify know which is the top level module or entity/architecture? –For Synthesis, Synplify scans the input source files from top to bottom of the source file list. For Verilog, the top level is the last “unreferenced” module it finds. This is the module that is not instantiated somewhere in the design. For VHDL, it is the last architecture of the last entity that it finds. Alternatively, one can specify the top module of the design using TCL scripts.

56. Synplicity Confidential FAQ(contd) Can I do incremental compiles? –Yes. This is a good method for bottom-up design and for debug during your development cycle. But we encourage you to synthesize the whole design in one shot once it is mostly complete. Since Synplify is extremely fast, you can easily synthesize the whole design frequently. This will let you more accurately see the size of and performance of the whole design and it lets Synplify do a better job of optimization. Please refer to on-line help for TCL commands that shows how to do incremental compiles.

57. Synplicity Confidential FAQ(contd) How do I compile a VHDL package into a library other than “work” ? –Just use the “set target library” menu, either from the “Target” pull down menu, or by clicking with the right mouse button when the cursor is over the package file in the Source Files window. What are project files? –Project files are ascii files that hold configuration information about your design. Project files in Synplify v3.0 are TCL based files.

58. Synplicity Confidential FAQ(contd) Can one specify I/O locations for top-level ports in Synplify? –Yes. Synplify supports the “xc_loc” string attribute that can be used to supply I/O locations for top level ports. This can be done using the “define_attribute” TCL command in the Synplify Design Constraints file (.sdc file ) or can be applied as meta-comment in verilog or attributes in VHDL source code itself.

59. Synplicity Confidential FAQ(contd) Does Synplify automatically do I/O synthesis? –Yes. Synplify automatically inserts I/O pads in the design. Synplify would also merge flipflops at the boundary into the I/Os via HDL instantiations. Additionally, the user may choose to manually insert I/Os. In that case, Synplify would only insert I/Os for pins that require them. If one does not want Synplify to automatically insert any I/Os, click the “Disable I/O Insertion” checkbox in the Synplify Set Device Options form.

60. Synplicity Confidential FAQ(contd) What kind of Xilinx Specific Attributes can be applied with Synplify? –syn_maxfan –syn_noclockbuf –xc_cmos/xc_ttl –xc_fast/xc_slow/xc_nodelay –xc_loc –xc_ioff –xc_alias –xc_props

61. Synplicity Confidential FAQ(contd) Why is Synplify so fast? –All synthesis algorithms were written from scratch. There was no use of decade-old algorithms which were more tuned for ASIC synthesis. –Superior technology mapping to xilinx base cells using Synplicity’s own Direct Synthesis Technology (DST). –Mapper is not “library” based. There is a mapper executable for each vendor Synplify supports which does superior technology mapping.

62. Synplicity Confidential FAQ(contd) Why does Synplify have the M1 switch for XC3000 devices? –With the current version (v3.0) of Synplify, choosing the M1 option for the XC3000 devices have no effect. We have included it to make the User interface consistent across all xilinx mappers. It would be used in the future if changes in the mapper are needed when there is M1 support for the XC3000 family of devices.

63. Synplicity Confidential FAQ(contd) How does Synplify handle asynchronous set/reset flipflops for xilinx 4000 architectures? –Xilinx xc4000 devices do not have asynchronous set/reset flipflops. We do not recommend using these types of flipflops. However, we do supply XNF netlists for a DFFRS constructed out of latches (LDCP_1). The latches themselves are constructed using cross-coupled gates. These XNF netlists are located in the synplcty\lib\xilinx directory.

64. Synplicity Confidential FAQ(contd) With v3.0/v3.0a of Synplify and M1 v1.3.7 there is a discrepancy in the number of FMAPs used. The M1 tools report more FMAPs than what Synplify reports. Why? –This is a bug in M1 v1.3.7. The Alliance Series 1.3.7 patch is now available for download from Xilinx ftp site. This patch solves the problem with inefficiency in packing FMAPs which lead to excessive area and delay in certain design implementations. The patch is available on all platforms and is located at ftp://ftp.xilinx.com/pub/swhelp/M1.3_alliance directory.

65. Synplicity Confidential FAQ(contd) How do I create black boxes in Verilog? Verilog Example: module myram(out, in, addr, we) /* synthesis black_box */ ; output [15:0] out; input [15:0] in; input [4:0] addr; input we; endmodule

66. Synplicity Confidential FAQ(contd) VHDL Example: library IEEE; use IEEE.std_logic_1164.all; use synplify.attributes.all; -- entity goes here architecture struct of top is component myram (outp: out std_logic_vector(15 downto 0); inp : in std_logic_vector(15 downto 0); addr: in std_logic_vector(4 downto 0); we: in std_logic); end component; attribute black_box of myram : component is true; begin -- architecture body here end struct;

67. Synplicity Confidential FAQ(contd) What kind of timing constraints can be applied? –define_input_delay –define_output_delay –define_reg_input_delay –define_reg_output_delay –define_clock –define_multicycle_path

68. Synplicity Confidential FAQ(contd) How do I simulate after synthesis? –Synplify v3.0 can write out mapped verilog/vhdl structural netlists for post-synthesis simulation. How do I disable false paths for the timing report or optimization? –There is currently no direct means to disable false paths from analysis. One can however supply constraints that effectively make paths from or to I/Os non-critical for synthesis.

69. Synplicity Confidential FAQ(contd) Does Synplify handle multi-cycle paths? –Yes. One can use the define_multicycle_path - from OR define_multicycle_path -to TCL based constraint commands to specify multicycle paths. Example: define_multicycle_path -to register_c 2

70. Synplicity Confidential FAQ(contd) How can one speed up a register to register path in Synplify? –To speedup a register to register path, one can use the define_reg_output_delay and define_reg_input_delay commands. define_reg_output_delay -improve define_reg_input_delay -improve -improve option restructures the design during optimization to help meet timing.

71. Synplicity Confidential FAQ(contd) Does Synplify support XBLOX? –Synplify does use XBLOX for the XC3000 devices. It does it own module generation for XC4000/E/EX/L/XL and XC5200 devices by mapping directly to Xilinx RPMs. Do I have to instantiate STARTUP blocks for Synplify? –No. Synplify automatically synthesizes the STARTUP blocks if it is appropriate for your design.

72. Synplicity Confidential Quiz-8 Synplify supports xilinx specific attributes that help designers to lock pins and use dedicated pads. The attribute can be applied as a meta-comment in the language itself. In the attached verilog model assign location information for xilinx place and route as follows: input data: P20,P91,P18,P17 output out : TL output cout : A1 on the module top_counter2. module top_counter2(out, cout, data, load, cin, clk,reset); output cout ; output [3:0] out ; input [3:0] data ; input load,cin,clk,reset; counter2 my_counter(.cout(cout),.out(out),.data(data),.load(load),.cin(cin),.clk(clk),.reset(reset)); endmodule

73. Synplicity Confidential Quiz-9 Synplify supports xilinx specific attributes that help designers to lock pins and use dedicated pads. You can use VHDL language attributes to apply the location information in the source VHDL file. In the attached vhdl model assign location information for xilinx place and route as follows: input data: P20,P91,P18,P17 output out : TL output cout : A1 on the entity top_counter2. entity top_counter is port (clk, reset, load: in std_logic; data: in std_logic_vector (3 downto 0); count: out std_logic_vector (3 downto 0) ); end top_counter; architecture arch1 of top_counter is begin my_counter: counter port map(clk,reset,load,data,count); end arch1;

74. Synplicity Confidential Quiz-10 Synplify distributes an import library containing all the xilinx primitives/macros and one can use this import library (xc4000.v/xc3000.v) to instantiate the xilinx primitives/macros in the source verilog file. In the RAM example below, how would you inform Synplify where the RAM32X1 macro is located. Assume you are targeting xc4000e devices and the import library file is located at c:\SYNPLCTY\lib\xilinx directory. module ram_32x8 (o,we,d,a); output [7:0] o; input we; input [7:0] d; input [4:0] a; RAM32X1 U0 (.O(o[0]),.D(d[0]),.WE(we),.A4(a[4]),.A3(a[3]),.A2(a[2]),.A1(a[1]),.A0(a[0])) ; RAM32X1 U1 (.O(o[1]),.D(d[1]),.WE(we),.A4(a[4]),.A3(a[3]),.A2(a[2]),.A1(a[1]),.A0(a[0])); RAM32X1 U2 (.O(o[2]),.D(d[2]),.WE(we),.A4(a[4]),.A3(a[3]),.A2(a[2]),.A1(a[1]),.A0(a[0])) ; RAM32X1 U3 (.O(o[3]),.D(d[3]),.WE(we),.A4(a[4]),.A3(a[3]),.A2(a[2]),.A1(a[1]),.A0(a[0])); RAM32X1 U4 (.O(o[4]),.D(d[4]),.WE(we),.A4(a[4]),.A3(a[3]),.A2(a[2]),.A1(a[1]),.A0(a[0])); RAM32X1 U5 (.O(o[5]),.D(d[5]),.WE(we),.A4(a[4]),.A3(a[3]),.A2(a[2]),.A1(a[1]),.A0(a[0])); RAM32X1 U6 (.O(o[6]),.D(d[6]),.WE(we),.A4(a[4]),.A3(a[3]),.A2(a[2]),.A1(a[1]),.A0(a[0])); RAM32X1 U7 (.O(o[7]),.D(d[7]),.WE(we),.A4(a[4]),.A3(a[3]),.A2(a[2]),.A1(a[1]),.A0(a[0])) ; endmodule

75. Synplicity Confidential Quiz-11 Synplify distributes an import library containing all the xilinx primitives/macros and one can use this import library (xc4000.vhd/xc3000.vhd) to instantiate the xilinx primitives/macros in the source verilog file. In the RAM example below, how would you inform Synplify where the RAM32X1 macro is located. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ram_32x1 is port (o : out std_logic; d,we,a4, a3, a2, a1, a0: in std_logic); end ram_32x1; architecture arch1 of ram_32x1 is begin u1: RAM32X1 port map (o,d,we,a4,a3,a2,a1,a0); end arch1;

76. Synplicity Confidential Quiz-12 Create a Synplicity constraint file (.sdc file) and define the clock frequency to be 75 MHz for the verilog module stub given below. Use the attributes supplied by Synplify to force a transition time of the output driver to be FAST. module prep3(CLK, RST, IN, OUT); input CLK, RST; input [7:0] IN; output [7:0] OUT; /* functionality descrobed here */; endmodule