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1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 5 Digital Building Blocks.

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1 1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 5 Digital Building Blocks

2 2 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.1 1-bit half adder

3 3 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.2 Carry bit

4 4 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.3 1-bit full adder

5 5 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.4 Carry propagate adder

6 6 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.5 32-bit ripple-carry adder

7 7 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.6 (a) 32-bit carry-lookahead adder (CLA), (b) 4-bit CLA block

8 8 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.7 16-bit prefix adder

9 9 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.8 Synthesized adder

10 10 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.9 Subtractor: (a) symbol, (b) implementation

11 11 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.10 Synthesized subtractor

12 12 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.11 4-bit equality comparator: (a) symbol, (b) implementation

13 13 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.12 N-bit magnitude comparator

14 14 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.13 Synthesized comparators

15 15 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.14 ALU symbol

16 16 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.15 N-bit ALU

17 17 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.16 4-bit shifters: (a) shift left, (b) logical shift right, (c) arithmetic shift right

18 18 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.17 Multiplication: (a) decimal, (b) binary

19 19 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.18 4  4 multiplier: (a) symbol, (b) function, (c) implementation

20 20 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.19 Synthesized multiplier

21 21 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.20 Array divider

22 22 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.21 Fixed-point notation of 6.75 with four integer bits and four fraction bits

23 23 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.22 Fixed-point representation of 2.375: (a) absolute value, (b) sign and magnitude, (c) two’s complement

24 24 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.23 Fixed-point two’s complement conversion

25 25 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.24 Addition: (a) binary fixed-point, (b) decimal equivalent

26 26 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.25 Floating-point numbers

27 27 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.26 32-bit floating-point version 1

28 28 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.27 Floating-point version 2

29 29 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.28 IEEE 754 floating-point notation

30 30 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.29 Floating-point addition

31 31 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.30 Counter symbol

32 32 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.31 N-bit counter

33 33 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.32 Synthesized counter

34 34 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.33 Shift register symbol

35 35 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.34 Shift register schematic

36 36 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.35 Shift register with parallel load

37 37 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.36 Synthesized shiftreg

38 38 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.37 Scannable flip-flop: (a) schematic, (b) symbol, and (c) N-bit scannable register

39 39 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.38 Generic memory array symbol

40 40 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.39 4  3 memory array: (a) symbol, (b) function

41 41 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.40 32 Kb array: depth = 2 10 = 1024 words, width = 32 bits

42 42 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.41 Bit cell

43 43 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.42 4  3 memory array

44 44 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.43 Three-ported memory

45 45 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.44 DRAM bit cell

46 46 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.45 DRAM stored values

47 47 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.46 SRAM bit cell

48 48 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.47 32  32 register file with two read ports and one write port

49 49 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.48 ROM bit cells containing 0 and 1

50 50 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.49 4  3 ROM: dot notation

51 51 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.50 4  3 ROM implementation using gates

52 52 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.51 Fuse-programmable ROM bit cell

53 53 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.52 4-word  1-bit memory array used as a lookup table

54 54 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.53 Synthesized ram

55 55 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.54 M  N  P-bit PLA

56 56 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.55 3  3  2-bit PLA: dot notation

57 57 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.56 3  3  2-bit PLA using two-level logic

58 58 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.57 General FPGA layout

59 59 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.58 Cyclone IV Logic Element (LE) (Reproduced with permission from the Altera Cyclone  IV Handbook 2010 Altera Corporation.)

60 60 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.59 LE configuration for two functions of up to four inputs each

61 61 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.60 LE configuration for one function of more than four inputs

62 62 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.61 LE configuration for FSM with two bits of state

63 63 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.62 ROM implementation: (a) dot notation, (b) pseudo-nMOS circuit

64 64 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.63 3  3  2-bit PLA using pseudo-nMOS circuits

65 65 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.64 Funnel shifter

66 66 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 5.65 ROM circuits

67 67 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 01

68 68 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 02

69 69 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 03

70 70 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 04

71 71 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 05

72 72 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 06

73 73 Copyright © 2013 Elsevier Inc. All rights reserved. UNN Figure 1

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