1. Scott Robinson Aaron Sikorski Peter Phelps

2.  Introduction  FIR Filter Design  Optimization  Application  Edge Detection  Sobel Filter  Communications  Design Process Flow  Conclusion

3.  Goal: Improve and apply our previously designed FIR Filter for a specific purpose. Implement design on NEXYS2 FPGA.  Requirements: The FPGA must communicate with a host PC through the USB interface.

4.  N-bit input values, M-bit tap values, K-bit taps  Modulated such that the Booth encoding and Wallace tree were both in a single module.

5.  Removed unnecessary pipelining in our full- adder module.  Changed our Booth constants to be generated on the tap values.  Moved the Booth encoding to outside of the Multiplier module.  Greatly reduced the area required while not sacrificing any speed by minimizing the replication of logic.

6. … Multiplier 1 Multiplier K Input [t]Input [t-K] Booth Encoder Wallace Tree Partial Product Generator Booth Encoder Wallace Tree Partial Product Generator … Multiplier 1 Multiplier K Tap 1 … Tap K Wallace Tree Partial Product Generator Wallace Tree Partial Product Generator Input [t]Input [t-K] Booth Encoder Old DesignNew Design

7. Old Design: New Design:

8.  Description of edge detection and why we chose it. Why is it important?

9.  What we used matlab for.

10.  Stucture of sobel filter.  Add a picture.

11.  Verilog code based on usbif_reg.  Uses a state machine to control input/output.  Instantiates a single Sobel filter.  Logic flow:  Store input into register array  Step inputs through Sobel filter and store output into separate register array  Output register array

12.  Uses C code which is based on usb_demo.  Sends sixty bytes continuously until EOF.  Stored the output of the FPGA into an array which is reconstructed into an image in MATLAB.  Note: Initial design sent and received one byte at a time which caused our design to be too slow. Once changing to the “sixty input – 20 output” design our speed reduced to under three minutes.

14. Questions?