1. Survey on Trace Analyzer (2) Hong, Shin 2015-10-201/34Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

2. Table of Contents  Introduction  Motivation  Simulation Trace Model  JMP A X  POTA  Further Study  References  Discussion 2015-10-202/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

3. Introduction1/4  The importance of Software is getting increased.  Quality assurance of the software is very important today.  Software are becoming more complex.  Concurrency with a large number of components  To assure correctness of a software,  Traditional Testing  Formal verification 2015-10-203/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

4. Introduction2/4  Traditional Testing  Can not prove the correctness of a software  Costs a lot of time  Model Checking  Labor-some process  Hard to assure the correctness of executable code  Costs a lot of time These are generally infeasible for a system with a large number of components and concurrency such as SoC. 2015-10-204/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

5. Introduction3/4  Trace Analyzer  Specify requirements in formal language.  Extract status of process while a target program is executing.  Verify whether the trace is satisfied against a given formal requirement.  Advantages  No labor-some job is needed.  Formal specifications can be used.  Possible to verify executable program. 2015-10-205/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

6. Introduction 4/4 Previously, TemporalROVER LTL, MTL was used. Java Path Explorer LTL was used.  Detect existing error in current executions. What about Java Path Explorer’s error pattern analysis? Deadlock analysis, Data race analysis 2015-10-206/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

7. Motivation1/6  Example : Landing airplane when the plane is landing, landing has been approved and radio signal is live. 2015-10-207/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

8. Motivation2/6 int landing=0, approved=0, radio=1 ; void thread1{ askLandingApproval() ; if (approved ==1) { landing=1; doLanding() ; landing=0; else printf(“Landing is not approved”);} void askLandingApproval() { if (radio == 0) approved = 0 ; else approved=1;} void thread2 { while(1) if (time_out) radio=0;} A bug exists 2015-10-208/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

9. Motivation3/6 In most cases 1)landing=0;radio=1;approved=0 2)if (radio == 1) 3)approved = 1 4)landing = 1 5)landing = 0 6)if (time_out) 7)radio = 0 ; Successful execution trace 2015-10-209/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

10. Motivation4/6 1)landing=0;1)if (time_out) 2)radio=1; 2)radio = 0 ; 3)approved=0; 4)if (radio==0) 5)approved=1; 6)landing=1 ;  Check whether every trace from asynchronous product of two traces is satisfied with given requirement. 2015-10-2010/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

11. Motivation5/6 1)landing=0; 2)radio=1; 3)approved=0; 4)if (radio==1) 5)approved=1; 6)landing=1 ; 7)if (time_out) 8)radio = 0 ;  Partial order traces can be used to simulate some total order trace. 2015-10-2011/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

12. Motivation6/6 (1) Specify formal requirement of a system. (2) Extract interesting temporal relations between processes as partial order traces. (3) Create partial order trace with respect to extracted information. (4) Check whether the model satisfies the requirement or not (simulating total order traces). 2015-10-2012/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

13. Simulation Trace Model1/5 For two distinguishable events e and f, e happens before f if and only if (1) e occurs before f in the same process. (2) e is sending a message and f is a receiving of that message. (3) There exist e happens before g and g happens before f.  Events in the same process are totally ordered and events between different processes are partially ordered. 2015-10-2013/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

14. Simulation Trace Model2/5 int x = 0 ; int y = 0 ; lock a ; void thread1 { a.acquire() ; x = 1 ; x = 2 ; a.release() ; } void thread2 { y = 1 ; a.acquire() ; y = 3 ; y = 4 ; a.release() ; } 2015-10-2014/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

15. Simulation Trace Model 3/5 int x = 0 ; int y = 0 ; lock a ; void thread1 {void thread2 { y = 1 ; a.acquire() ; x = 1 ; x = 2 ;a.acquire() ; a.release() ; a.acquire() ; }y = 3 ; y = 4 ; a.release() ; } 2015-10-2015/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

16. Simulation Trace Model 4/5  Vector clocks  Represent the happen before relation  A vector clock assigns timestamps to events such that the partial order relation between events can be determined by using the timestamps. Given a compuation G on n process v : V(G) → N n such that for all events e and f, e happens before f if and only if e.v ≤ f.v 2015-10-2016/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

17. Simulation Trace Model5/5 int x = 0 ; int y = 0 ; lock a ; void thread1{[1,0][0,1] void thread2 { [0,2] y = 1 ; a.acquire() ;[2,0] x = 1 ;[3,0] x = 2 ;[4,0] a.release() ;[5,0] [2,3]a.acquire() ; }[2,4]y = 3 ; [2,5]y = 4 ; [2,6]a.release() ; } 2015-10-2017/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

18. JMP A X1/3  Java MultiPathExplorer, JMP A X  Extend Java PathExplorer  Combine testing and formal methods techniques.  Possible to reveal errors in multithreaded programs that are hard to detect by observing successful executions. 2015-10-2018/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

19. JMP A X2/3 2015-10-2019/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

20. JMP A X3/3  Use past time LTL to specify safety properties.  Predict safety errors from successful executions.  Check a simulation trace model in a exhaustive way. O(|E| n ) where E is events in each process and n is the number of processes. 2015-10-2020/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

21. POTA1/11  Partial Order Trace Analyzer  Create a model from partial order traces  State Explosion - Regular CTL - Computation slicing 2015-10-2021/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

22. POTA2/11 2015-10-2022/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

23. POTA3/11  The order on events must be a partial order.  For a directed graph G that represent the computation, A global state(consistent cut) on G as - a subset of vertices s.t. if the subset contains a vertex then it contains all its incoming neighbors. - denoted by the set of its frontier. - ⊥ i for initial state of process i, ⊤ i for final state of process i C (G) is the set of global states on the graph G. - it forms a distributive lattice under subset relation. 2015-10-2023/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

24. POTA4/11 2015-10-2024/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

25. POTA5/11  Predicate Detection problem Given a distributive lattice L =( C (G), ⊆ ) and a temporal logic predicate p, decide whether L,{ ⊥ } ⊧ p holds or not. 2015-10-2025/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

26. POTA6/11  A predicate is regular if, given two consistent cuts that satisfy the predicate, the consistent cuts obtained by their set union and set intersection also satisfy the predicate. Predicate p is regular iff ( C satisfy p ) and ( D satisfy p )  ( C ∩ D satisfy p ) and ( C ∪ D satisfy p ) 2015-10-2026/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

27. POTA7/11  Temporal logic : safety and liveness property  Computational Tree Logic(CTL)  Path quantifier A: all full pathsE: some full path  Temporal logicG:alwaysF:eventuallyX:next time  Non-temporal predicates : λ : C → P (AP) where AP is atomic propositions AG(p), AF(p), EG(p), EF(p), EX(p), EX(p)[i], AX(p) where p is a non-temporal predicate. 2015-10-2027/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

28. POTA8/11 2015-10-2028/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

29. POTA9/11 2015-10-2029/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

30. POTA10/11  RCTL  A sublogic of CTL contains regular non-temporal logics and regular temporal logic. If p is a regular non-temporal logic then EF(p), AG(p),EG(p), and EX(p)[j] is also regular. Express both safety property and liveness property. 2015-10-2030/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

31. POTA11/11  Computation Slice  All consistent cuts of a computation that satisfy a given predicate.  A slice of a computation with respect to a predicate exists iff the set of global states that satisfy the predicate forms a sub- lattice of the lattice of global states  As long as predicate is regular, there exists efficient algorithm to compute the slice for regular predicate. O(|p|n 2 |E|) 2015-10-2031/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

32. Further study POTA - Regular predicates - Detection of global predicate More survey on trace analyzer 2015-10-2032/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

33. References  [1] Leslie Lamport, Time, Clocks, and the Ordering of Events in a Distributed System, 1978.  [2] V K.Garg et al, On Slicing a Distributed Computation, 1999.  [3] K Sen et al, Runtime Safety Analysis of Multithreaded Programs, 2003.  [4] A Sen&V K. Garg, Partial Order Trace Analyzer for Distributed Programs, 2003.  [5] A Sen&V K.Garg, Formal Verification of Simulation Traces Using Computation Slicing, 2006. 2015-10-2033/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST

34. Discussion 2015-10-2034/34 Survey on Trace Analyzer (2) Hong,Shin@PSWLab KAIST