1. Paper Review Avelino Zepeda Martinez High Performance Reconfigurable Pipelined Matrix Multiplication Module Designer

2. Usage –Communication Systems –Signal and Video Processing Issues –Operations of square matrices increase as functions of n 3  Area  Speed  Power 2.- Background

3. 3.- Matrix Multiplication

4. 4.- Matrix Multiplication (Cont.)

5. Basic Matrix Multiplication block using d t Can perform any matrix multiplication –Inefficient 5.- Matrix Multiplication (Cont.)

6. Three types of errors –Number Representation  ADCs  Sampling Rate  Available Bits –Rounding Error  Round to Nearest Even (RNE)  Round Towards Zero, or Truncation (TRA)  Round Down (Floor)  Round Up (Ceiling)  Round Away from Zero –Algorithm/Design Error 6.- Error Analysis

7. 7.- Error Analysis (Cont.)

8. Reconfigurable Matrix Multiplication Module Designer (RMD) –Designed in Pearl scripting language –Outputs:  RTL of Multiplication Module  Testbench  MATLAB files  Modelsim verification files –Designed to output RTL for FPGA and VLSI 8.- Design Overview

9. Three main sections –Module Designer –Area, Speed, and Error Analysis –High Speed Memory Interface 9.- RMD FPGA Design Flow

10. Main Design Outputs RTL –Matrix Multiplication Processing Unit (MMPU) –Memory Interface –Control Unit (CU) 10.- Module Designer

11. RTL created for 2x2 matrix to 2048x2048 matrix Composed of: –Matrix Multiplier Block (p-MMB) –Internal Logic 11.- Module Designer (MMPU)

12. Bottom-Up Design Approach Start with 2-MMB, or 2X2, which is the pipelined version of d t Insert adders after 2 -MMB blocks 12.- Module Designer (p-MMB)

13. 13.- Module Designer (p-MMB Cont.)

14. 14.- Module Designer (Memory Interface)

15. Can be created for Fixed or Variable Operation Size Designed to use Finite State Machine For variable size each operation size has a sub-FSM 15.- Module Designer (Control Unit)

16. RMD also generates MATLAB and Testbench files –Improves accuracy of output Matrix –Reduces design and verification time MATLAB creates data files for the Testbench –Maximum input values supported  Bit size: 64 bits  Matrix Size: 2048 x 2048  Test Vectors: 100 Data tested on Testbench using Modelsim 16.- Area, Speed, and Error Analysis

17. 17.- Area, Speed, and Error Analysis (Cont.)

18. RMD calculates the estimated area –Area = Matrix Multiplier Block + Memory + Control These calculations use: –n:Maximum Matrix Multiplication Size –r:Input bits –p:Matrix Multiplier Block Size –M r :r-bit Multiplier –A r :r-bit Adder –R r :r-bit Register –Mux r :r-bit ( 2-1 ) Mux –RNE:( 2 r+k max to r) bit Rounding –HA:Half Adder –Mem r :r-bit Memory –FF:Flip Flops –F max :Maximum Frequency 18.- Area, Speed, and Error Analysis (Cont.)

19. 19.- Area, Speed, and Error Analysis (Cont.)

20. 20.- Area, Speed, and Error Analysis (Cont.)

21. 21.- Area, Speed, and Error Analysis (Cont.)

22. Two Native Port Interfaces –Interface with DDR 2 memory –Width of 64 bits –Supports Back-to-Back Transfers –Transfer Sizes:  Byte  Half-word  Word  4 -word and 8 -word cache line  16 -word, 32 -word, and 64 -word bursts 22.-High Speed Memory Interface

23. 23.- Area Results (Spartan 3 E)

24. 24.- Area Results (Virtex- 5 )

25. 25.- Time Results

26. Design Pipelined –Increase Throughput and Reduce Operation Latency Incremental Adder –Reduce Area and Increase Accuracy Modifiable –Increased Accuracy –Faster Operation –Lower Area 26.- Conclusion