1. MICROCONTROLLERS
8051

2. WHAT IS A MICROCONTROLLER?
All of the components needed for a controller were built right onto one chip.
A microcontroller is a highly integrated chip which includes, on one chip, all or most of the parts needed for a controller.
The microcontroller could be called a "one-chip solution".

3. MICROPROCESSOR vs MICRO CONTROLLER

4. Features : The Intel 8051 is used in embedded systems 8-bit CPU
4k bytes ROM for the program
128 BYTES of RAM
32 I/O lines ( 4 PORTS WITH 8 EACH )
2 timers
1 Serial port
6 interrupt sources
Low cost (10-15 cents per chip)

5. Block Diagram Interrupt Control 4k ROM 128 bytes RAM Timer 1 Timer 2
External Interrupts
Interrupt
Control 4k
ROM
128 bytes
RAM
Timer 1
Timer 2
CPU
OSC
Bus
Control
4 I/O Ports
Serial
P0 P2 P P3
TXD
RXD
Addr/Data

6. 8051 – PIN DIAGRAM

7. 8051 – 40 PIN IC

8. 8051 contains four I/O ports (P0 - P3)
Each port can be used as input or output (bi-direction)
Port 0
P0（P0.0～P0.7）
8-bit R/W - General Purpose I/O
Or acts as a multiplexed low byte address and data bus for external memory design
Port 1
P1（P1.0～P1.7）
Only 8-bit R/W - General Purpose I/O
Port 2
P2（P2.0～P2.7）
Or high byte of the address bus for external memory design
Port 3
P3（P3.0～P3.7）
General Purpose I/O
if not using any of the internal peripherals (timers) or external interrupts.

9. PORT 3 – MULTIPLE FUNCTIONS

10. IMPORTANT PINS
PSEN (out): Program Store Enable, the read signal for external program memory (active low).
ALE (out): Address Latch Enable, to latch address outputs at Port0 and Port2
EA (in): External Access Enable, active low to access external program memory locations 0 to 4K
RXD,TXD: UART pins for serial I/O on Port 3
XTAL1 & XTAL2: Crystal inputs for internal oscillator.

11. SIGNALS - OPERATION Vcc（pin 40）：
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND（pin 20）：ground
XTAL1 and XTAL2（pins 19,18）：
These 2 pins provide external clock.
using a quartz crystal oscillator

12. QUARTZ CRYSTAL OSCILLATOR
Using a quartz crystal oscillator
We can observe the frequency on the XTAL2 pin. C2
30pF C1
XTAL2
XTAL1
GND

13. RST - RESET The high pulse must be high at least 2 machine cycles.
RST（pin 9）：reset
input pin and active high
The high pulse must be high at least 2 machine cycles.
power-on reset.
Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost.
Reset values of some 8051 registers

14. RESET Value of Some 8051 Registers:PC
0000
ACC
0000 B
0000
PSW
0000 SP
0007
DPTR
0000
RAM are all zero

15. RESET CIRCUITARY
EA/VPP X1 X2
RST
Vcc
10 uF
8.2 K
30 pF 9 31

17. BLOCK DESCRIPTION ACCUMULATOR ( ACC ) B REGISTER Operand register
Implicit or specified in the instruction
Has an address in on chip SFR bank
B REGISTER
to store one of the operands for multiplication and division
otherwise, scratch pad
considered as a SFR

18. PROGRAM STATUS WORD ( PSW )
Set of flags contain status information
One of the SFR
STACK POINTER ( SP )
8 bit wide register
Incremented before data is stored on to the stack using PUSH or CALL instructions
Stack defined anywhere on the 128 byte RAM
RESET  initiated to 0007H
Not a top to down structure
Allotted an address in SFR

19. PORT 0 TO 3 LATCHES & DRIVERS
DATA POINTER ( DPTR )
16 bit register
contains DPH and DPL
Pointer to external RAM address
DPH and DPL allotted separate addresses in SFR bank
PORT 0 TO 3 LATCHES & DRIVERS
Each i/o port allotted a latch and a driver
Latches allotted address in SFR
User can communicate via these ports
P0, P1, P2,P3

20. SERIAL DATA BUFFER TIMER REGISTERS
internally had TWO independent registers
TRANSMIT buffer parallel in serial out ( PISO )
RECEIVE buffer  serial in parallel out (SIPO)
identified by SBUF and allotted an address in SFR
byte written to SBUF  initiates serial TX
byte read from SBUF  reads serially received data
TIMER REGISTERS
for Timer0 ( 16 bit register – TL0 & TH0 )
for Timer1 ( 16 bit register – TL1 & TH1 )
four addresses allotted in SFR

21. OSCILLATOR
generates basic timing clock signal using crystal oscillator
INSTRUCTION REGISTER
decodes the opcode and gives information to timing and control unit
EPROM & PROGRAM ADDRESS REGISTER
provide on chip EPROM and mechanism to address it
All versions don’t have EPROM
RAM & RAM ADDRESS REGISTER
provide internal 128 bytes RAM and a
mechanism to address internally

22. ALU
Performs 8 bit arithmetic and logical operations over the operands held by TEMP1 and TEMP 2
User cannot access temporary registers
SFR REGISTER BANK
set of special function registers
address range : 80 H to FF H

23. INSTRUCTIONS SET ARITHMETIC INSTRUCTIONS LOGIC INSTRUCTIONS
BOOLEN INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
SINGLE BIT INSTRUCTIONS
JUMP,LOOP AND CALL INSTRUCTIONS

24. Arithmetic instructions
8051 INSTRUCTION SET
Arithmetic instructions
ADD,SUB,DIV,MUL,INC,DEC
IIE - SAP

25. ADD & SUB
add a, byte ; a  a + byte addc a, byte ; a  a + byte + C These instructions affect 3 bits in PSW: C = 1 if result of add is greater than FF AC = 1 if there is a carry out of bit 3 OV = 1 if there is a carry out of bit 7, but not from bit 6, or visa versa.

26. ADD Example
What is the value of the C, AC, OV flags after the second instruction is executed?
mov a, #3Fh
add a, #D3h
C = 1
AC = 1
OV = 0

27. Subtract Example: Example: Clr c SUBB A, #0x4F ;A  A – 4F
SUBB A, byte
subtract with borrow
Example:
SUBB A, #0x4F ;A  A – 4F – C
Notice that
There is no subtraction WITHOUT borrow.
Therefore, if a subtraction without borrow is desired,
it is necessary to clear the C flag.
Example:
Clr c
SUBB A, #0x4F ;A  A – 4F

28. Increment & Decrement
INC A
increment A
INC byte
increment byte in memory
INC DPTR
increment data pointer
DEC A
decrement accumulator
DEC byte
decrement byte
The increment and decrement instructions do NOT affect the C flag.
Notice we can only INCREMENT the data pointer, not decrement.

29. SIGNIFICANCE OF carry flag
Assume 16-bit word in R3:R mov a, r2
add a, #1 ; use add rather than increment to affect C
mov r2, a
mov a, r3
addc a, #0 ; add C to most significant byte
mov r3, a

30. Multiply MUL AB ; BA  A * B
When multiplying two 8-bit numbers, the size of the maximum product is 16-bits
FF x FF = FE01
(255 x 255 = 65025)
MUL AB ; BA  A * B
Note : B gets the High byte
A gets the Low byte

31. Integer Division Division DIV AB ; divide A by B A  Quotient(A/B)
B  Remainder(A/B)
OV - used to indicate a divide by zero condition.
C – set to zero

32. Decimal Adjust DA a ; decimal adjust a
Used to facilitate BCD addition.
Adds “6” to either high or low nibble after an addition to create a valid BCD number.
Example:
mov a, #23h
mov b, #29h
add a, b; a  23h + 29h = Ch(wanted 52)
DA a ; a  a + 6 = 52

33. BOOLEAN INSTRUCTIONS
CLR,CPL,SETB,AND,OR

34. BOOLEAN INSTRUCTIONS This group includes:
This group of instructions is associated with the single-bit operations of the 8051.
This group allows manipulating the individual bits of bit addressable registers and memory locations as well as the CY flag.
The P, OV, and AC flags cannot be directly altered.
This group includes:
Set, clear, and, or complement, move.
Conditional jumps.

35. CLR <bit> CLR C CLR bit
CLR instruction can operate on the carry flag
CLR C
The CARRY flag is set to 0
CLR instruction can operate on any directly addressable
bit
CLR P2.7
If Port 2 has been previously written with DCH ( ),
then the operation leaves the port set to 5CH ( )

36. SETB <bit> SETB C SETB bit
SETB instruction operates on the carry flag and sets the specified bit to 1
SETB C
sets the carry flag to 1
SETB instruction operates on any
directly-addressable bit and sets the specified bit to 1
SETB P2.0
Port 2 has the value of 24H ( ), the Port 2 value changes to 25H ( )

37. CPL <bit> CPL C CPL bit
This operation complements the carry flag
CPL C
CPL instruction complements any directly addressable Bit
CPL P2.2
If Port 2 has the value of 53H ( ) then after the execution the port set to 55H ( )

38. ANL ANL C, <source-bit> ANL C, /<source-bit>
This instruction ANDs the bit addressed with the carry bit and stores the result in the carry bit itself
ANL C,P2.7 ;AND carry flag with bit 7 of P2
If a slash (/) is used in the source operand bit, the logical complement of the source bit is used, but the source bit itself is not affected
ANL C,/OV ;AND with inverse of OV flag

39. ORL ORL C, <source-bit> ORL C, /<source-bit>
This instruction ORs the bit addressed with the carry bit and stores the result in the carry bit itself
ORL C,P2.5 ;OR carry flag with bit 5 of P2
If a slash (/) is used in the source operand bit, the logical complement of the source bit is used, but the source bit itself is not affected
ORL C,/OV ;OR with inverse of OV flag

40. MOV <dest-bit>,<source-bit>
One of the operands must be the carry flag; the other may be any directly-addressable bit
MOV C,P3.3
MOV P2.0,C
If P2=C5H ( ), P3.3=0 and CY=1 initially, after instructions, P2=C4H ( ) and CY=0

41. JC / JNC addr Jump to a relative address if CY is set / cleared.
MOV A,#20H
JC ARRAY1
SUBB A,R0
CLR C
JNC ARRAY2

42. JB / JNB <bit>,addr
Jump to a relative address if a bit is set / cleared.
JB ACC.7,AR1
JB P1.2,AR2
JNB ACC.6, RY1
JNB P1.3,RY2

43. JBC <bit>,addr
Jump to a relative address if a bit is set and clear the bit.
JBC P1.3,ARRAY1
If P1=56H ( ), the above instruction sequence will cause the program to branch to the instruction at ARRAY1, modifying P1 to 52H ( )

44. 8051 - INSTRUCTION SET CALL, JMP, RET
BRANCH INSTRUCTIONS
CALL, JMP, RET
IIE - SAP

45. Branching instructions
Program branching instructions are used to
control the flow of actions in a program
Some instructions provide decision making capabilities and transfer control to other parts of the program.
e.g. conditional and unconditional branches

46. CALL  ACALL & LCALL
The 8051 provides 2 forms for the CALL instruction:
Absolute Call – ACALL
Uses an 11-bit address
The subroutine must be within the same 2K page.
Long Call – LCALL
Uses a 16-bit address
The subroutine can be anywhere.
Both forms push the 16-bit address of PC on the stack and update the stack pointer.

47. Absolute Call – ACALL addr11
This instruction unconditionally calls a subroutine indicated by the address
2 byte instruction: The upper 3-bits of the address combine with the 5-bit opcode to form the 1st byte and the lower 8-bits of the address form the 2nd byte
Eg. ACALL LOC_SUB
If SP=07H initially
label “LOC_SUB” is at memory 0567H,
then executing instruction at 0230H (PC),
SP=09H, internal RAM locations 08H and 09H will contain 32Hand 02H respectively and PC=0567H

48. LONG CALL - LCALL addr16
It is a Long call, the subroutine may therefore begin anywhere in the full 64 kB program memory address space
3 byte instruction
LCALL LOC_SUB
Initially, SP=07H
label “LOC_SUB” is at memory 4100H
Executing the instruction at 0230H ( PC),
SP=09H, internal RAM locations 08H and 09H contain 33H and 02H respectively and PC=4100H

49. RETURN  RET & RETI
The 8051 provides 2 forms for the return instruction:
Return from subroutine – RET
Pop the return address from the stack and continue execution there.
Return from ISR – RETI
Pop the return address from the stack.
Restore the interrupt logic to accept additional interrupts at the same priority level as the one just processed.
Continue execution at the address retrieved from the stack.
The PSW is not automatically restored.

50. JUMP SJMP
The 8051 provides four different types of unconditional jump instructions:
Short Jump – SJMP addr
Uses an 8-bit signed offset relative to the 1st byte of the next instruction.
the range of destination allowed is from to+127 bytes from the instruction
SJMP RELSRT
If the label RELSRT is at program memory location 0120H and the SJMP instruction is located at address 0100H ( PC) ,after executing the instruction, PC=0120H

51. JUMP  LJMP the LJMP instruction at location 0120H (PC)
Long Jump – LJMP
Uses a 16-bit address.
3 byte instruction capable of referencing any location in the entire 64K of program memory.
LJMP FAR_ADR
If the label FAR_ADR is at program memory location 3456H
the LJMP instruction at location 0120H (PC)
After instruction, it loads the PC with 3456H

52. JUMP  AJMP Absolute Jump – AJMP AJMP NEAR Uses an 11-bit address.
2 byte instruction
The 11-bit address is substituted for the lower 11-bits of the PC to calculate the 16-bit address of the target.
The location referenced must be within the 2K Byte
AJMP NEAR
If the label NEAR is at program memory location 0120H, the AJMP instruction at location 0234H (PC) loads the PC with 0120H

53. Indirect Jump If the ACC=02H, execution jumps to LOC2
This instruction adds the 8-bit unsigned value of the ACC to the 16-bit data pointer and the resulting sum is returned to the PC
Neither ACC nor DPTR is altered
No flags are affected
MOV DPTR, #LOOK_TBL
+ DPTR
LOOK_TBL: AJMP LOC0
AJMP LOC1
AJMP LOC2
If the ACC=02H, execution jumps to LOC2
AJMP is a two byte instruction

54. CONDITIONAL JUMP
The 8051 supports different conditional jump instructions.
ALL conditional jump instructions use an 8-bit address.
Jump on Zero – JZ / JNZ
Jump if the A == 0 / A != 0
The check is done at the time of the instruction execution.
Jump on Carry – JC / JNC
Jump if the C flag is set / cleared.

55. CONDITIONAL JUMP Jump on Bit – JB / JNB
Jump if the specified bit is set / cleared.
Any addressable bit can be specified.
Jump if the Bit is set then Clear the bit – JBC
Jump if the specified bit is set.
Then clear the bit.

56. Compare and Jump if Not Equal – CJNE
Compare the magnitude of the two operands and jump if they are not equal.
The values are considered to be unsigned.
The Carry flag is set / cleared appropriately.
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel

57. Decrement and Jump if Not Zero – DJNZ
Decrement the first operand by 1 and jump to the location identified by the second operand if the resulting value is not zero.
DJNZ 20H,LOC1
DJNZ 30H,LOC2
DJNZ 40H,LOC3
If internal RAM locations 20H, 30H and 40H contain the values 01H, 5FH and 16H respectively,
the above instruction sequence will cause a jump to the instruction at LOC2, with the values 00H, 5EH, and 15H in the 3 RAM locations

58. NOP This is the no operation instruction
The instruction takes one machine cycle operation time
Hence it is useful to time the ON/OFF bit of an output port
CLR P1.2
NOP
SETB P1.2

59. 8051 INSTRUCTION SET AND,OR,NOT,XOR,ROTATE,SWAP
LOGICAL INSTRUCTIONS
AND,OR,NOT,XOR,ROTATE,SWAP
IIE-SAP

60. Logic Instructions Bitwise logic operations Clear Rotate Swap
(AND, OR, XOR, NOT)
Clear
Rotate
Swap
Logic instructions do NOT affect the flags in PSW

61. Bitwise Logic ANL  AND ORL  OR XRL  XOR CPL  Complement 00001111
Examples:
ANL  AND
ORL  OR
XRL  XOR
CPL  Complement
ANL
ORL
XRL
CPL

62. anl PSW, #0xE7 ;PSW AND 11100111 orl PSW, #0x18 ;PSW OR 00011000
xrl P1, #0x40 ;P1 XRL

63. Other Logic Instructions
CLR - clear
RL – rotate left
RLC – rotate left through Carry
RR – rotate right
RRC – rotate right through Carry
SWAP – swap accumulator nibbles

64. CLR ( Set all bits to 0) CLR A CLR byte (direct mode)
CLR Ri (register mode)
(register indirect mode)

65. Rotate Rotate instructions operate only on a RL a RR a
Mov a,#0xF0 ; a
RR a ; a
RR a
RR a ; a

66. Rotate through Carry RRC a RLC a C mov a, #0A9h ; a  A9
add a, #14h ; a  BD ( ), C0
rrc a ; a  , C1
RLC a
mov a, #3ch ; a  3ch( )
setb c ; c  1
rlc a ; a  , C1 C C

67. Swap
SWAP a
mov a, #72h ; a  27h
swap a ; a  27h

68. Rotate and Multiplication/Division
Note that a shift left is the same as multiplying by 2, shift right is divide by 2
mov a, #3; A (3)
clr C ; C 0
rlc a ; A (6)
rlc a ; A (12)
rrc a ; A (6)

69. Serial Communication

70. Ways of Data Transfer Computers transfer data in two ways: Parallel
Often 8 or more lines (wire conductors) are used to transfer data to a device that is only a few feet away.
Serial
To transfer to a device located many meters away, the serial method is used. The data is sent one bit at a time.

71. Parallel Transfer
Serial Transfer

72. Serial Communication b/w micro controller & LCD.

73. Serial Communication is Sending of data from transmitter to receiver bit-by-bit.

74. Advantages of Serial Communication
For long distances.
Low Cost.
Disadvantages of Serial Communication
The speed of serial Communication is very slow than parallel communication.

75. ULN 2003
ULN 2003 is used to drive the Actuator. The Actuator used in this project is Stepper Motor.
Pin Diagram of ULN 2003

76. CKT. Diagram of ULN 2003 with Stepper Motor

77. Application of ULN 2003
To control stepper motor , DC motor. Servomotor.
To operate Relays.

78. How to use KEIL c Double Click on the icon present on the desktop.
STEPS TO ACCESS µVISION:
Double Click on the icon present on the desktop.
The following window will be popped-up

79. 3. click on “project” and select “new project”
4. Create a new folder of your project name.
5. Select “New” from “File” menu.
6. And save file as “file_name.c” i.e. save file with “.c” extension.

80. 7. Select device for target as shown in figure below.
8. Configure Device and select clock MHZ.

82. 9.Create HEX. File.

83. 10. Press right click and select “INSERT #include<REGF51.H>”.

84. 11. Type the application code and after compiling, saving the code burn it into controller using
“Flash Mazic”.