1. TSC 12/03 Post-CMOS Grand Challenges Juri Matisoo Vice-President, Technology Semiconductor Industry Association

2. TSC 12/03 Acknowledgements  SIA TSC Working Group  Bob Doering, TI, Chair;  George Bourianoff, Intel  Philip Wong, IBM  Luan Tran, Micron  Papu Maniar, Motorola  Jim Hutchby, SRC

3. TSC 12/03 Agenda/Overview  Value and Need for Investment in Nanoelectronics* Research  Long-Term Manufacturing Research  Long-Term Device Research  Recommendations Summary * In this presentation: “nanoelectronics” ≡ “future IC technology”

4. TSC 12/03 Benefits to the U.S. from the Semiconductor Industry  Powers other Industries  Spurs Economic Growth  ~3% of GDP growth due to “computer quality” increase  Creates High-Wage Jobs  ~300K jobs in the U.S. currently  Fosters International Competitive Advantage  Bolsters National Defense/Homeland Security  Intelligence gathering/processing  Guidance/Control systems (e.g., for E2C2)  Logistics management/efficiency  Communications Technology

5. TSC 12/03 The Need for New Enablers of Progress in Future ICs  The industry productivity gains of 25%/year reduction in cost/function and improved performance and reduced power consumption over the last 40 years have been driven by miniaturization of semiconductor devices.  The International Technology Roadmap for Semiconductors (ITRS) predicts that over the next 10-15 years, this trend will end.  New devices and manufacturing techniques are needed.

6. TSC 12/03 Long-Range Grand Challenges  In the long term, the SIA TSC feels that we face two grand challenges worthy of very large federal funding: (1)Scaling limits of “evolutionary lithography/thin-film manufacturing” (2)Scaling limits of “charge-transport devices/interconnect”  We suggest that these might be overcome through new and synergistic research in the under-funded broad areas of: (1)“Directed self-assembly” of complex structures with “nanoelectronics-functionality” (computation, comm., etc.) (2)“Beyond (classical) charge transport” signal-processing/ computational technology (e.g., based on quantum-states)

7. TSC 12/03 Rationale for Directed Self-Assembly Break the manufacturing “scaling tyranny” of: (1)Maintaining adequate process-control margin (2)Contamination-density-limited yield (3)Escalating wafer-fab capital cost (4)Lengthening production cycle time (5)Rapidly increasing photomask cost

8. TSC 12/03 Desired Consequences of Directed Self-Assembly (1)Approaching “atomic-level” perfection/control in manufacturing of nano-systems (“future SOCs”) (2)Providing radically enhanced and affordable functionality in nano-systems (3)Revolutionizing fab economics and logistics (4)Application to a broad range of devices (e.g., from “ultimate CMOS” to “quantum-state”)  Note: the principal barrier to implementation of advanced device concepts is often “manufacturing feasibility”

9. TSC 12/03 Current Examples of Self-Assembly Techniques

10. TSC 12/03 The Self-Assembly “Place and Route” Problem

11. TSC 12/03

13. IC Metrics that Should Guide Research on NanoManufacturing  Cost/Integrated-Function(e.g., $/gate or $/bit integrated into system)  Operations/Second(computation speed, e.g. MIPS)  Power Dissipation(both operating and standby power)  Integration Density(e.g., integrated functions/cm 2 or /cm 3 )  Integration Diversity(SOC functions - e.g., analog, RF, e-RAM)  Capital Cost/Capacity (e.g., capital investment $/chips/month)  Mfg. Cycle Time(impacts time-to-market and ASIC delivery)  R&D Cost(e.g., cost per new product or tech node) NanoManufacturing Goals: 100x beyond limits of the evolutionary approach

14. TSC 12/03 Rationale for Beyond-Charge-Transport Signal-Processing/Computation Break the “CMOS electrical scaling tyranny,” e.g.: (1)Voltage (limiting speed/power/error-rate tradeoff) (2)Resistance (limiting speed and low power) (3)Capacitance (limiting speed and low active power) (4)Charge-Leakage Mechanisms (limiting standby power)

15. TSC 12/03 Desired Consequences of Beyond-Charge-Transport Computation/Signal-Processing (1)Providing significant performance improvements via mechanisms beyond merely scaling physical dimensions (e.g., multiple logic states, far-from- equilibrium operation) (2)Providing qualitatively new types of nano-system functionality (e.g., direct sensing/actuating)

16. TSC 12/03 Some Potential State Variables Alternative to Classical Electric Charge  Atomic/molecular quantum states (including “artificial atoms”)  Magnetic-dipole magnitude/orientation (e.g., electron/nuclear spin)  Electric-dipole magnitude/orientation  Magnetic flux quanta  Photon number  Photon polarization  Mechanical state

17. TSC 12/03 Example: Spin-Resonance Transistor (SRT) Example: Spin-Resonance Transistor (SRT)  Transistors that control spins rather than charge  More energy efficient than conventional transistors  Combines magnetic and electrostatic fields  May enable quantum computing Courtesy Eli Yablanovitch, UCLA

18. TSC 12/03 Challenges to Metrology  Instrumentation and techniques for  Identification and visualization of atomic species and structure  Observation of short-range and long-range order, defects  Device characterization

19. TSC 12/03 Summary  We have identified two major challenges for nanoelectronics, worthy of significant Government funding via NNI  We presented these findings to PCAST as part of their NNI review, and strategy development