1. Ceng 450 Project

2. Pinout of Processor Interrupt is optional Processor in_port[7:0] out_port[7:0] clock rst interrupt

3. Instruction Format Three types of instructions A-Format e.g. arithmetic instructions B-Format e.g. branch instructions L-Format e.g. load and store instructions

4. A-Format Instructions Arithmetic Instructions: Op-Code 74 ra 32 rb 1 0 e.g.: ADD R[2], R[1] 010010 01 74 32 10

5. B-Format Instructions Branch Instructions: Op-Code 74 brx 32 rb 1 0 e.g.: Br R[3] 100100 11 74 32 10

6. Subroutine … br.sub … return subroutine:

7. Subroutine Link Register (LR): a dedicated register for subroutine call&return br.sub: PC+1 is loaded into LR … br.sub … return subroutine: 1C LR: 0X1B: 1B PC: PC+1 0X1C:

8. Subroutine LR: a dedicated register for br.sub instructions br.sub: PC+1 is loaded into LR return: PC is loaded with LR … br.sub … return subroutine: 1C LR: 0X1B: 9B PC: 0X9B: 0X1C:

9. Subroutine LR: a dedicated register for br.sub instructions br.sub: PC+1 is loaded into LR return: PC is loaded with LR … br.sub … return subroutine: 1C LR: 0X1B: 1C PC: 0X9B: 0X1C:

10. L-Format Load/Store Instructions: Op-Code 74 ra 32 1 0 e.g.: load R[2], 0xA2 000110 00 74 32 10 ea/imm First address: Second address: A2

11. Project A processor that executes every program written in the instruction set

12. Processor Architecture 1)Datapath Includes components, alu, register file, memory, … 2)Controller Controls flow of instruction and data in datapath Datapath Controller

13. Instruction Memory Memory We need a container to hold instructions

14. Register File Memory Reg File A place for R[0]~R[3]

15. Alu ALU Memory Reg File A unit for arithmetic calculations

16. Data Memory ALU Memory Reg File Memory A unit that holds data

17. Pipeline Architecture Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM To break critical path

18. 5-Stages Datapath Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Up to now, design of main components

19. 5-Stages Datapath Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Up to now, design of main components Complete the datapath for every instruction gradually

20. 5-Stages Datapath Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Up to now, design of main components Complete the datapath for every instruction gradually e.g. ADD instruction

21. PC A component that holds address of Inst. Memory (PC) Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address

22. Fetch Memory PC AddressInstruction 0 IF/ID Register Op-Code 7 4 ra 3 2 1 rb

23. ADD Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address Datapath

24. Decode Reg File 0 IF/ID Register Op-Code 7 4 ra 3 2 1 rb rd_index1 rd_index2 2 2 ID/EX rd_data1 rd_data2 RD1 RD2 8 8

25. ADD Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address Datapath

26. Execution Stage ALU ID/EX RD1 RD2 EX/MEM AR op1 op2 Alu Result mode

27. ADD Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address

28. Memory Access Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address AR

29. Write Back Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address AR

30. Write Back Write Back ID/EX MEM/WB AR Reg File rd_index1 rd_index2 rd_date1 rd_data2 Write Data

31. Write Back Write Back ID/EX MEM/WB AR Reg File Register No.1 Register No.2 Data Register 1 Data Register 2 Write Data Which register ADD R[2], R[1]

32. Revising Our Design Memory Address Instruction 0 IF/ID Register Op-Code 7 4 ra 3 2 1 rb

33. Write Back Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address AR ra Data

34. Write Back Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address AR ra Data

35. Write Back Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address AR ra Data ra

36. Write Back Memory Access Write Back Instruction Fetch Decode Execute ALU Memory Reg File Memory IF/ID ID/EX MEM/WB EX/MEM Address AR ra Register No. Data ra

37. Other Instructions We should repeat similar steps for other instructions

38. Controller 0 Op-Code 7 4 ra 3 2 1 rb rd_index1 rd_index2 2 2 rd_date1 rd_data2 DR1 DR2 Controller ALU Mode Register File Mem Opr WB Opr

39. Execute ALU ID/EX DR2 EX/MEM AR op1 Alu Result ALU Mode Mem Opr WB Opr Mem Opr WB Opr DR1

40. Mem Data Memory Access Memory Access Memory EX/MEM MEM/WB Mem Opr WB Opr ADD R[2], R[1] Mem Opr: Write_En = 0 Mem Adr Wr_En

41. Write Back Memory Access Write Back Decode Execute ALU Reg File Memory ID/EX EX/MEM AR ra Register No. ra WB Opr Register Value wr_en

42. Controller Design Controller Base on Control Signals in Data-Path Control Signals To DataPath Components Flags Instruction from IR

43. State Machine rst reset=1 decode Op=add Op=load … Deactivate control signals wr_enable =1

44. State Machine Implementation parameter [3:0] RESET=0,DECODE=1; always @(negedge clk) if(rst) begin state = RESET; //deactivate all control signals end else begin case(state) RESET:begin state=DECODE; end DECODE: begin if(opcode=ADD) … end default: state=RESET; endcase end rst reset=1 decode Op=add Op=load

45. Implementation Strategy First Design Datapath Design Controller base on Data-Path Connect Controller and Data-Path

46. Designing Datapath Necessary Components Program Counter Instruction/Data Memory ALU Register File ….

47. Datapath Hierarchy Data Path ALUPCMemory Register File Mux Start your design from Bottom Modules

48. Simulate each Component Post-Route Simulation ALU Add 01110111 01000110 111101101 Is it Correct? Test Vectors

49. Wiring CPU (Top Module) Controller Reg. File Memory PC ALU Data Signals Control Signals Data Path

50. Debugging Hazards Because of Pipeline Data Hazard Control Hazard Simulating Complete CPU Implementation (Pin Assignment)