1. © 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction Purpose  This course provides an overview of the CPU architecture of the MCUs in the M16C/2x and M16C/6x series. Objectives  Learn about the register set.  Review the memory map and the data arrangement in memory and registers.  Understand the operating states and special modes, including the Wait and Stop power-down modes. Content  23 pages  5 questions Learning Time  35 minutes

2. © 2008, Renesas Technology America, Inc., All Rights Reserved 2 M16C MCU Platform Ultra Performance 32-bit Performance 16-bit “Sweet Spot” 8- to 16-bit Transition Platform Entry Device High Performance Performance Point 8-bit 16-bit 32-bit M32C Core M32C/10x M32C/8x M16C/6x M16C/2x R8C M32C/9x Covered in the R8C Architecture Courses Covered in M16C Architecture Courses

3. © 2008, Renesas Technology America, Inc., All Rights Reserved 3 Basic Features Register architecture –Four 16-bit data registers  or four 8-bit and two 16-bit registers  or two 32-bit registers –Two 16-bit address registers –Two 16-bit base registers –Two stack pointer registers –One flag/status register –A 20-bit program counter (1Megabyte address space) –A 20-bit vector interrupt table 91 basic instructions –Hardware multiplier—standard in the M16C CPU core 8 standard addressing modes Up to 24MHz operation – 41.6ns execution of shortest instruction Low-power modes General-Purpose Registers

4. © 2008, Renesas Technology America, Inc., All Rights Reserved M16C/60 CPU Core/Register Model R0HR0L R1HR1L R2 R3 A0 A1 FB 08 / 0 0 0 0 0 16 / 0 015 31 / 15 15 15 / 7 7 7 8 bits 16 bits SB 015 ISP USP 0 015 FLG PC INTB 0 0 0 19 15 Data Registers 2 x 32-bit registers ( R0R2, R1R3 ) or 4 x 16-bit registers ( R0, R1, R2, R3 ) or 4 x 8-bit registers ( R0L, R0H, R1L, R1H ) Address Registers 2 x 16-bit Address / General-Purpose Register A0, A1 1 x 32-bit Address Register [ A0A1 ] Base Registers SB and FB registers can be used in indexed addressing modes (e.g., C-language stack frame addressing) Control Registers 2 stack pointers allow H/W interrupt stack and OS stack Flag Register – Condition flags and interrupt priority 20-bit Program Counter Interrupt Table Pointer allows multiple Interrupt Vector Tables 20 bits

5. © 2008, Renesas Technology America, Inc., All Rights Reserved M16C Register Bank 0 and 1 R0HR0L R1HR1L R2 R3 A0 A1 FB 08 / 0 0 0 0 0 16 / 0 015 31 / 16 15 15 / 7 7 7 R0H R0L R1HR1L R2 R3 A0 A1 FB 08 / 0 0 0 0 0 16 / 0 015 31 / 15 15 15 / 7 7 7 SB 015 ISP USP 0 015 FLG PC INTB 0 0 019 15 Bank 0 – Active when bank bit “B” in flag register = 0 (default state) Bank 1 – Active when bank bit “B” in flag register = 1 Single set of registers, always active regardless of bank bit “B”

6. © 2008, Renesas Technology America, Inc., All Rights Reserved FLG IPLUIOBSZDC b15 b0 : Reserved area IPL : Processor interrupt priority level (Interrupt Priority Level) Level 0 to 7 set by software or hardware. U : Stack pointer select flag (When U=0, the ISP is selected; when U=1, the USP is selected.) I : Interrupt enable flag (When I=1, the interrupt is enabled.) O : Overflow flag (This bit is set when an arithmetic operation produces an overflow.) B : Register bank select flag (When B=0, register bank 0 is selected; when B=1, register bank 1 is selected. ) S : Sign flag (This bit is set when an arithmetic operation results in a negative value; otherwise, this bit is 0. ) Z : Zero flag (This bit is set when an arithmetic operation results in 0; otherwise, this bit is 0. ) D : Debug flag (This flag enables a single-step interrupt. When D=1, a single-step interrupt is generated after an instruction is executed. When an interrupt is acknowledged, this flag is cleared to 0.) C : Carry flag (This flag holds a carry, borrow, or shifted-out bit that has occurred in the arithmetic/logic unit.) Configuration of Flag Register

8. © 2008, Renesas Technology America, Inc., All Rights Reserved 8 Data Arrangement in Memory  M16C CPU core is little- Endian (low byte first). This means that the low byte of a multi-byte value is stored in the lowest memory address.  Addresses are stored as three bytes. The uppermost 4 bits of DATA(H) are ignored. N N+1 N+2 N+3 b0b7 Byte (8-bit) data DATA N N+1 N+2 N+3 b0b7 Word (16-bit) data DATA(L) DATA(H) N N+1 N+2 N+3 b0b7 Address ( 20-bit) data DATA(L) N N+1 N+2 N+3 b0b7 Long Word (32- bit) data DATA(LL) DATA(LH) DATA(M) DATA(H) DATA(HL) DATA(HH)

9. © 2008, Renesas Technology America, Inc., All Rights Reserved 9 Memory-to-Register Data Moves MOV.B N,R0H MOV.W N,R0 N N+1 N+2 N+3 b0b7 Byte (8-bit) data DATA N N+1 N+2 N+3 b0b7 Word (16-bit) data DATA(L) DATA(H) b0 L H R0 b15 Does not change b0 L H R0 b15

10. © 2008, Renesas Technology America, Inc., All Rights Reserved 10 Microprocessor mode is selected by hardware (CNVss Pin ). Memory-expansion mode is selected by software in Single-chip mode. When CNVss = L, the MCU will exit Reset in Single-chip mode, executing from user flash. M16C Memory Maps Single-chip mode SFR area Internal RAM area Prohibited Internal Flash area Memory-expansion mode SFR area Internal RAM area External area Internal Flash area Microprocessor mode SFR area Internal RAM area External area 00000H 00400H FFFFFH External area 07FFFH

12. © 2008, Renesas Technology America, Inc., All Rights Reserved 12 Instruction Cycle, Memory Access  An instruction cycle is equal to the CPU clock cycle time. –In divide-by-1 mode, single-cycle instructions execute in one Xin clock period (e.g., with a 20MHz oscillator circuit, the shortest instruction executes in 50ns).  Accesses to internal RAM and Flash are single cycle–except SFR accesses, which are always two cycle.  External memory read accesses are one cycle unless Wait States are added.  External memory writes are two cycles unless Wait States are added. – At full clock speeds, memory timing may require that Wait States be inserted for reads and/or writes.

13. © 2008, Renesas Technology America, Inc., All Rights Reserved 13 Operating Modes and Transitions RESET NORMAL MODE 8 MEDIUM SPEED HIGH SPEED, MEDIUM SPEED LOW SPEED, LOW POWER DISSIPATION sub-clock RING OSCILLATOR STOP MODE WAIT MODE All Oscillators Stopped CPU Clock Stopped

14. © 2008, Renesas Technology America, Inc., All Rights Reserved 14 Normal Mode In Normal mode, the CPU executes user code; clock sources for the CPU are:  Main Clock—Xin - Crystal or resonator input - Many devices have PLLs, allowing multiplication of this clock signal - Xin can be divided by 1, 2, 4, 8 or 16 to be used as CPU clock - Divide-by-8 is the default CPU clock speed  Sub-Clock—XCin - Low-speed crystal - 32kHz, typical - Can be used as CPU clock  Ring Oscillator (standard in newer M16C/2x and M16C/6x MCUs) - Can be used as CPU clock

15. © 2008, Renesas Technology America, Inc., All Rights Reserved 15 Wait Mode Executing a WAIT Instruction stops BCLK (CPU core clock). Peripheral Clocks will continue to run unless configured to stop by a control bit in the System Clock Register. - Peripherals using subclock will still receive clock. Wait mode and a timer running from the sub-clock can implement a real-time clock function with typical power supply current of 2µA. An interrupt or Reset is used to exit Wait mode.

17. © 2008, Renesas Technology America, Inc., All Rights Reserved 17 Wait Mode Transitions RESET NORMAL MODE 8 MEDIUM SPEED HIGH SPEED, MEDIUM SPEED LOW SPEED, LOW POWER DISSIPATION sub-clock RING OSCILLATOR STOP MODE WAIT MODE WAIT INSTRUCTION INTERRUPT WAIT INSTRUCTION WAIT INSTRUCTION WAIT INSTRUCTION

18. © 2008, Renesas Technology America, Inc., All Rights Reserved 18 Stop Mode Entered by setting the “Stop All Clocks” bit in the clock control register Disables the oscillator circuits Peripherals are disabled because there are no clocks, but:  Timers can be used to count external pulses  UARTs and Serial I/Os can be used with external clocks  Timer or UART/SIO can generate an interrupt to exit Stop mode Typical power supply current is well below 1µA An Interrupt or Reset is used to exit Stop mode

19. © 2008, Renesas Technology America, Inc., All Rights Reserved 19 Stop Mode RESET NORMAL MODE 8 MEDIUM SPEED HIGH SPEED, MEDIUM SPEED LOW SPEED, LOW POWER DISSIPATION sub-clock RING OSCILLATOR INTERRUPT STOP ALL CLOCK BIT SET STOP ALL CLOCK BIT SET STOP ALL CLOCK BIT SET STOP MODE WAIT MODE STOP ALL CLOCK BIT SET

20. © 2008, Renesas Technology America, Inc., All Rights Reserved 20 Flash MCU Power Consumption * VccOperating Mode ClockIcc* (typical) Power Consumption* 5V Normal20MHz16mA80mW Wait32kHz2.0µA10µW Stop______0.8µA4µW 3V Normal10MHz8mA24mW Wait32kHz1.8µA5.4µW Stop_______0.7µA2.1µW * Data shown is for an M16C/26 device

23. © 2008, Renesas Technology America, Inc., All Rights Reserved 23 Course Summary Overview of the general features of the M16C architecture Register set Memory map and data arrangement in memory and registers Operating states and state transitions Power-down modes