1. ECE291 Lecture 9 Interrupts I

2. ECE 291 Lecture 9Slide 2 of 28 Lecture Outline Printed lab manual?Printed lab manual? Interrupt I/OInterrupt I/O Interrupt vectorsInterrupt vectors Software interruptsSoftware interrupts Hardware interruptsHardware interrupts 8259 Programmable Interrupt Controller8259 Programmable Interrupt Controller Interrupt PriorityInterrupt Priority Writing your own ISRsWriting your own ISRs

3. ECE 291 Lecture 9Slide 3 of 28 Interrupt Driven I/O Consider an I/O operation, where the CPU constantly tests a port to see if data is availableConsider an I/O operation, where the CPU constantly tests a port to see if data is available CPU polls the port if it has data available or can accept data CPU polls the port if it has data available or can accept data Polled I/O is inherently inefficientPolled I/O is inherently inefficient Program may check port more often than necessary  wastes CPU cycles Program may check port more often than necessary  wastes CPU cycles Program may also not check port enough  loses data Program may also not check port enough  loses data Analogy: Checking your watch every 5 minutes until class is over (NEVER in this class though I bet), or continuously opening up the door to see if your friends are coming Analogy: Checking your watch every 5 minutes until class is over (NEVER in this class though I bet), or continuously opening up the door to see if your friends are coming Solution is to provide interrupt driven I/OSolution is to provide interrupt driven I/O Perform regular work until an event occurs Perform regular work until an event occurs Process event when it happens, then resume normal activities Process event when it happens, then resume normal activities Analogy: Alarm clock, doorbell, telephone ring Analogy: Alarm clock, doorbell, telephone ring

4. ECE 291 Lecture 9Slide 4 of 28 Interrupts Triggers that cause the CPU to perform various tasks on demandTriggers that cause the CPU to perform various tasks on demand Three kinds:Three kinds: Software interrupts – initiated by the INT instruction Software interrupts – initiated by the INT instruction Hardware interrupts – originate in peripheral hardware Hardware interrupts – originate in peripheral hardware Exceptions – occur in response to error states in the processor Exceptions – occur in response to error states in the processor Regardless of source, they are handled the sameRegardless of source, they are handled the same Each interrupt has a unique interrupt number from 0 to 255. These are called interrupt vectors. Each interrupt has a unique interrupt number from 0 to 255. These are called interrupt vectors. For each interrupt vector, there is an entry in the interrupt vector table. For each interrupt vector, there is an entry in the interrupt vector table. The interrupt vector table is simply a jump table containing segment:offset addresses of procedures to handle each interrupt The interrupt vector table is simply a jump table containing segment:offset addresses of procedures to handle each interrupt These procedures are called interrupt handlers or interrupt service routines (ISR’s) These procedures are called interrupt handlers or interrupt service routines (ISR’s)

5. ECE 291 Lecture 9Slide 5 of 28 Interrupt Vectors The first 1024 bytes of memory (addresses 00000 – 003FF) always contain the interrupt vector table. Always.The first 1024 bytes of memory (addresses 00000 – 003FF) always contain the interrupt vector table. Always. Each of the 256 vectors requires four bytes—two for segment, two for offsetEach of the 256 vectors requires four bytes—two for segment, two for offset Memory address (hex) Interrupt function pointer 003FC 4 * x 00008 00004 00000 INT 255 INT x INT 2 INT 1 INT 0

6. ECE 291 Lecture 9Slide 6 of 28 Software Interrupts The operating system has handlers for many interrupts. These routines provide various built-in functions:The operating system has handlers for many interrupts. These routines provide various built-in functions: Displaying text to the screen Displaying text to the screen File I/O File I/O Rebooting the system Rebooting the system Changing video modes Changing video modes Accessed with the INT instructionAccessed with the INT instruction

7. ECE 291 Lecture 9Slide 7 of 28 Software Interrupts Essentially just function calls using a different instruction to do the callingEssentially just function calls using a different instruction to do the calling Software interrupts give you access to “built-in” code from BIOS, operating system, or peripheral devicesSoftware interrupts give you access to “built-in” code from BIOS, operating system, or peripheral devices Use the INT instruction to “call” these functionsUse the INT instruction to “call” these functions

8. ECE 291 Lecture 9Slide 8 of 28 System BIOS Functions All PCs come with a BIOS ROM (or EPROM).All PCs come with a BIOS ROM (or EPROM). The BIOS contains procedures that provide basic functions such as bootstrapping and primitive I/O.The BIOS contains procedures that provide basic functions such as bootstrapping and primitive I/O. INT 19h: Reboot system INT 19h: Reboot system INT 11h: Get equipment configuration INT 11h: Get equipment configuration INT 16h: Keyboard I/O INT 16h: Keyboard I/O

9. ECE 291 Lecture 9Slide 9 of 28 Video BIOS Functions Video cards come with procedures stored in a ROMVideo cards come with procedures stored in a ROM Collectively known as the video BIOSCollectively known as the video BIOS Located at C0000-C7FFF and holds routines for handling basic video adapter functionsLocated at C0000-C7FFF and holds routines for handling basic video adapter functions To execute a function in video BIOS ROM, do an INT 10h with video sub-function number stored in AXTo execute a function in video BIOS ROM, do an INT 10h with video sub-function number stored in AX INT 10h, Sub-function examplesINT 10h, Sub-function examples AH=0, AL=2h: 80 column x 25 row text display mode AH=0, AL=2h: 80 column x 25 row text display mode AH=0, AL=13h: 320x200 pixel, 256-color graphics display mode AH=0, AL=13h: 320x200 pixel, 256-color graphics display mode

10. ECE 291 Lecture 9Slide 10 of 28 DOS Function Dispatcher INT 21h is the DOS function dispatcher. It gives you access to dozens of functions built into the operating system.INT 21h is the DOS function dispatcher. It gives you access to dozens of functions built into the operating system. To execute one of the many DOS functions, you can specify a sub- function by loading a value into AH just before calling INT 21To execute one of the many DOS functions, you can specify a sub- function by loading a value into AH just before calling INT 21 INT 21h sub-functionsINT 21h sub-functions AH=3Dh: Open File AH=3Dh: Open File AH=3Fh: Read File AH=3Fh: Read File AH=3Eh: Close File AH=3Eh: Close File AH=13h: Delete File AH=13h: Delete File AH=2Ah: Get system date AH=2Ah: Get system date AH=2Ch: Get system time AH=2Ch: Get system time AH=2Ch: Read DOS Version AH=2Ch: Read DOS Version AH=47h: Get Current Directory AH=47h: Get Current Directory AH=48h: Allocate Memory block (specified in paragraphs==16 bytes) AH=48h: Allocate Memory block (specified in paragraphs==16 bytes) AH=49h: Free Memory block AH=49h: Free Memory block AH=4Ch: Terminate program (and free resources) AH=4Ch: Terminate program (and free resources)

11. ECE 291 Lecture 9Slide 11 of 28 The INT and IRET Instructions Syntax: INT imm8Syntax: INT imm8 Imm8 is an interrupt vector from 0 to 255Imm8 is an interrupt vector from 0 to 255 INT does the following:INT does the following: Pushes flag register (pushf) Pushes flag register (pushf) Pushes return CS and IP Pushes return CS and IP Far jumps to [0000:(4*imm8)] Far jumps to [0000:(4*imm8)] Clears the interrupt flag disabling the interrupt system Clears the interrupt flag disabling the interrupt system IRET is to INT what RET is to CALLIRET is to INT what RET is to CALL Pops flag register Pops flag register Performs a far return Performs a far return

12. ECE 291 Lecture 9Slide 12 of 28 Things to Notice The interrupt vector table is just a big permanently located jump tableThe interrupt vector table is just a big permanently located jump table The values of the jump table are pointers to code provided by the BIOS, hardware, the OS, or eventually youThe values of the jump table are pointers to code provided by the BIOS, hardware, the OS, or eventually you Interrupt service routines preserve the flags as well as the registers they modify because the entire state of the computer must be completely unaltered by an ISRInterrupt service routines preserve the flags as well as the registers they modify because the entire state of the computer must be completely unaltered by an ISR

13. ECE 291 Lecture 9Slide 13 of 28 Hardware Interrupts Alert the processor of some hardware situation that needs tending to:Alert the processor of some hardware situation that needs tending to: A key has been pressed A key has been pressed A timer has expired A timer has expired A network packet has arrived A network packet has arrived Same software calling protocolSame software calling protocol Additional level of complexity with the interrupt “call” not coming from your program codeAdditional level of complexity with the interrupt “call” not coming from your program code Can happen at any time during the execution of your programCan happen at any time during the execution of your program

14. ECE 291 Lecture 9Slide 14 of 28 The 80x86 Interrupt Interface Device generates request signalDevice generates request signal Device supplies interrupt vector number on data busDevice supplies interrupt vector number on data bus Processor completes the execution of current instruction and executes ISR corresponding to the interrupt vector number on the data busProcessor completes the execution of current instruction and executes ISR corresponding to the interrupt vector number on the data bus ISR upon completion acknowledges the interrupt by asserting the INTA signalISR upon completion acknowledges the interrupt by asserting the INTA signal 80x86 processor Some device INT Request (INTR) INT Acknowledge (INTA) Data bus

15. ECE 291 Lecture 9Slide 15 of 28 The 80x86 Interrupt Interface The previous setup could get complicated with multiple devices generating multiple interrupts connected to the same few pins on the processorThe previous setup could get complicated with multiple devices generating multiple interrupts connected to the same few pins on the processor Solution: the 8259 Programmable Interrupt ControllerSolution: the 8259 Programmable Interrupt Controller

16. ECE 291 Lecture 9Slide 16 of 28 The 8259 PIC 8259 PIC 0 1 2 3 4 5 6 7 INTR INTA INT# 80x86 Interrupt outputs from peripheral devices

17. ECE 291 Lecture 9Slide 17 of 28 The 8259 PIC The PIC is programmed with a base interrupt vector numberThe PIC is programmed with a base interrupt vector number “0” corresponds to this base “0” corresponds to this base “1” corresponds to this base + 1 “1” corresponds to this base + 1 “n” corresponds to this base + n “n” corresponds to this base + n For example, if the PIC is programmed with a base interrupt vector of 8, then “0” corresponds to interrupt vector 8For example, if the PIC is programmed with a base interrupt vector of 8, then “0” corresponds to interrupt vector 8

18. ECE 291 Lecture 9Slide 18 of 28 Typical System Configuration Master 8259 INTR 0123456701234567 Slave 8259 INTR 0123456701234567 IRQ0 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 80x86 Base vector is 68h Base vector is 08h

19. ECE 291 Lecture 9Slide 19 of 28 Typical IRQ Assignments IRQ 0: Timer (triggered 18.2/second) IRQ 1: Keyboard (keypress) IRQ 2: Slave PIC IRQ 3: Serial Ports (Modem, network) IRQ 5: Sound card IRQ 6: Floppy (read/write completed) IRQ 8: Real-time Clock IRQ 12: Mouse IRQ 13: Math Co-Processor IRQ 14: IDE Hard-Drive Controller

20. ECE 291 Lecture 9Slide 20 of 28 Interrupt Priority Lower interrupt vectors have higher priorityLower interrupt vectors have higher priority Lower priority interrupts normally cannot interrupt higher priority interruptsLower priority interrupts normally cannot interrupt higher priority interrupts ISR for INT 21h is running ISR for INT 21h is running Computer gets request from device attached to IRQ8 (INT 78h)Computer gets request from device attached to IRQ8 (INT 78h) INT 21h procedure must finish before IRQ8 device can be servicedINT 21h procedure must finish before IRQ8 device can be serviced ISR for INT 21h is running ISR for INT 21h is running Computer gets request from Timer 0 IRQ0 (INT 8h)Computer gets request from Timer 0 IRQ0 (INT 8h) Code for INT 21h gets interrupted, ISR for timer runs immediately, INT21h finishes afterwardsCode for INT 21h gets interrupted, ISR for timer runs immediately, INT21h finishes afterwards

21. ECE 291 Lecture 9Slide 21 of 28 Preemptive/Non-Preemptive A preemptive interrupt is one that can be interrupted by another interrupt (i.e. one of higher priority)A preemptive interrupt is one that can be interrupted by another interrupt (i.e. one of higher priority) A non-preemptive interrupt is one that cannot be interrupted by another interruptA non-preemptive interrupt is one that cannot be interrupted by another interrupt How can an interrupt “become” non-preemptive?How can an interrupt “become” non-preemptive? CLI – CLear Interrupt flag – disables interrupts CLI – CLear Interrupt flag – disables interrupts STI – SeT Interrupt flag – enables interrupts STI – SeT Interrupt flag – enables interrupts

22. ECE 291 Lecture 9Slide 22 of 28 Preemptive/Non-Preemptive Making interrupts behave as non-preemptive:Making interrupts behave as non-preemptive: Software interrupts CLI INT xx STI Software interrupts CLI INT xx STI Hardware Interrupts My_ISR CLI STI IRET Hardware Interrupts My_ISR CLI STI IRET

23. ECE 291 Lecture 9Slide 23 of 28 Interrupt Priority Example

24. ECE 291 Lecture 9Slide 24 of 28 Interrupt Service Routines Reasons for writing your own ISR’sReasons for writing your own ISR’s to supersede the default ISR for internal hardware interrupts (e.g., division by zero) to supersede the default ISR for internal hardware interrupts (e.g., division by zero) to chain your own ISR onto the default system ISR for a hardware device, so that both the system’s actions and your own will occur on an interrupt (e.g., clock-tick interrupt) to chain your own ISR onto the default system ISR for a hardware device, so that both the system’s actions and your own will occur on an interrupt (e.g., clock-tick interrupt) to service interrupts not supported by the default device drivers (a new hardware device for which you may be writing a driver) to service interrupts not supported by the default device drivers (a new hardware device for which you may be writing a driver) to provide communication between a program that terminates and stays resident (TSR) and other application software to provide communication between a program that terminates and stays resident (TSR) and other application software

25. ECE 291 Lecture 9Slide 25 of 28 Interrupt Service Routines ISRs are meant to be shortISRs are meant to be short keep the time that interrupts are disable and the total length of the service routine to an absolute minimum – you do not want to block interrupts of lower priority! keep the time that interrupts are disable and the total length of the service routine to an absolute minimum – you do not want to block interrupts of lower priority! ISRs can be interruptedISRs can be interrupted ISRs must be in memoryISRs must be in memory Option 1: Redefine interrupt only while your program is running Option 1: Redefine interrupt only while your program is running the default ISR will be restored when the executing program terminatesthe default ISR will be restored when the executing program terminates Option 2: Use DOS Terminate-and-Stay-Resident (TSR) command to load and leave program code permanently in memory Option 2: Use DOS Terminate-and-Stay-Resident (TSR) command to load and leave program code permanently in memory

26. ECE 291 Lecture 9Slide 26 of 28 Servicing an Interrupt Complete current instructionComplete current instruction Preserve current contextPreserve current context PUSHF Store flags to stack PUSHF Store flags to stack Clear Trap Flag (TF) & Interrupt Flag (IF) Clear Trap Flag (TF) & Interrupt Flag (IF) Store return address to stack PUSH CS, PUSH IP Store return address to stack PUSH CS, PUSH IP Identify SourceIdentify Source Read 8259 PIC status register Read 8259 PIC status register Determine which device (N) triggered interrupt Determine which device (N) triggered interrupt Activate Interrupt Service RoutineActivate Interrupt Service Routine Use N to index vector table Use N to index vector table Read CS/IP from table Read CS/IP from table Jump to instruction Jump to instruction Execute Interrupt Service RoutineExecute Interrupt Service Routine usually the handler immediately re- enables the interrupt system (to allow higher priority interrupts to occur) (STI instruction) usually the handler immediately re- enables the interrupt system (to allow higher priority interrupts to occur) (STI instruction) process the interrupt process the interrupt Indicate End-Of-Interrupt (EOI) to 8259 PICIndicate End-Of-Interrupt (EOI) to 8259 PIC mov al, 20h mov al, 20h out 20h, al out 20h, al ;transfers the contents of AL to I/O port 20h Return (IRET)Return (IRET) POP IP (Far Return) POP IP (Far Return) POP CS POP CS POPF (Restore Flags) POPF (Restore Flags)

27. ECE 291 Lecture 9Slide 27 of 28 Timer Interrupt Example The ISR will count the number of timer interrupts receivedThe ISR will count the number of timer interrupts received The main program will use this count to display elapsed time in minutes and secondsThe main program will use this count to display elapsed time in minutes and seconds http://courses.ece.uiuc.edu/ece291/lecture/timer.exehttp://courses.ece.uiuc.edu/ece291/lecture/timer.exehttp://courses.ece.uiuc.edu/ece291/lecture/timer.exe

28. ECE 291 Lecture 9Slide 28 of 28 Timer interrupt – ISR code ;====== ISR Code ========= myint pushds;Save all registers pushax movax, cs;Load default segment movds, ax pushf;Call Orig Function w/flags callfar [oldv];Far Call to existing routine incword [count] ;Increment Interrupt count cmpword [count],18 jne.myintdone incword [scount];Next second movword [count], 0 cmpword [scount], 60 jne.myintdone incword [mcount]; Next minute movword [scount], 0.myintdone moval, 20h;Reset the PIC out20h, al;End-of-Interrupt signal popax;Restore all Registers popds iret;Return from Interrupt