2. GRECO - CIn - UFPE1 A Reconfigurable Architecture for Multi-context Application Remy Eskinazi Sant´Anna Federal University of Pernambuco – UFPE GRECO – Engineering Computer Group

3. GRECO - CIn - UFPE2 Motivation Hardware/Software Codesign platform for fast prototyping of digital systems Education Hardware/Software Codesign Reconfigurable systems Industrial prototyping of digital systems

4. GRECO - CIn - UFPE3 Chameleon Design Flow System Specification Partitioning HW/SW  Vision/51 Keil debugging Software algorithm Compilation Executable code CHAMELEON board Hardware description Behavioural Synthesis RT description Logic Synthesis (Netlist) Mapping VHDL C simulation

5. GRECO - CIn - UFPE4 Hw/Sw Configuration programs flow Keil Compiler Keil Compiler Source - C.hex.bin Parser Source - vhdl XILINX tools XILINX tools.hex.bin Parser software hardware Merge.mrg

6. GRECO - CIn - UFPE5 Codesign Architecture Biosensors Image Process Signal Process Acoustic Biosensor Temperature Reconfigurable Core Interfaces  C Hardware FPGA Core Selector Codesing Architecture bitstream PC (Database) Serial

7. GRECO - CIn - UFPE6 Chameleon Architecture EPROM (64K) host Serial comm. Shared memory data address FPGA (84 pins) 61 I/O ports XC4003E->XC4013 software hardware Microcontroller 80C32 80C51 87C51.......... 8 16 RAM (64K) RD WR INT0 ALE PEN WS BUSY/RDY INIT DONE PROG

8. GRECO - CIn - UFPE7 Hardware Reconfigurable Component XC4000 XILINX Architecture I/O Blocks (IOBs) D Q Slew Rate Control Passive Pull-Up, Pull-Down Delay Vcc Output Buffer Input Buffer Q D Pad D Q SD RD EC S/R Control D Q SD RD EC S/R Control 1 1 F' G' H' DIN F' G' H' DIN F' G' H' H Func. Gen. G Func. Gen. F Func. Gen. G4 G3 G2 G1 F4 F3 F2 F1 C4C1C2C3 K Y X H1 DIN S/R EC Configurable Logic Blocks (CLBs) Component 40003E 4005 4006 4008E 4010E 4013E Logic Cells 238 466 608 770 950 1,368 Max Logic Gates 3K 5K 6K 8K 10K 13K

9. GRECO - CIn - UFPE8 Monitor Program AnotherFile? Core Download End File? Yes Ram Not Configure FPGA Not Switch Executecode End Software and hardware cores Monitor transfer control to the application Returns to monitor Application

10. GRECO - CIn - UFPE9 Monitor Program 2kbytes 56kbytes (Hardware Cores) 2kbytes... Core 2 Core 1 Monitor variables monitor mirror User program Vectors (Sofware Cores) Core N

11. GRECO - CIn - UFPE10 Chameleon Supervisory

12. GRECO - CIn - UFPE11 Chameleon Board

13. GRECO - CIn - UFPE12 Conclusions A flexible low cost prototyping board has been developed; The platform shows to able to implement small designs in a hardware/software codesign approach; The board has shown to be able to reduce the time during the development process of digital systems ; Academic case studies has been implemented on the platform.

14. GRECO - CIn - UFPE13 (4) (5) (7) (6) (9) ) Chameleon Platform ) Oscillator Circuit Board ) Circuit Power Board ) Reset System ) Power On/Off ) Serial Communication ) Crystal Resonant Reference ) Crystal Resonant Work ) FIA System FIGURE 7 - Case study architecture (8) (3) AC / DC (1) ChameleonI FPGA Oscillator (2)