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Published byEvan Black Modified over 9 years ago
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Team Members Xuan Bao Jacob Cox Bryan Fleming Wenzhong Wu 20 February 2009
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Switch Fabric moves frames from Receive to Transmit Uses information from (and provides information to) Table Management Must be faster for more ports and higher line speeds Three common designs…
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Interfaces with Receive Ports Consists of two components ◦ Receive Interface (Bryan Fleming) ◦ Receive Handler (Xuan Bao)
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Arbitrates between Receive Ports needing service Round-robin service policy ◦ Valid for 4-port switch with fabric running at 4x line speed
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Block Diagram
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Interface Interfaces to Receiver Interface: Output: Data_Read: out std_logic; --read enable signal to Rcv FIFO, handshake Length_Read: out std_logic; -- read enable signal to Rcv length FIFO Packet_Finished: out std_logic; handshake --packet end signal Packet_ Error: out std_logic; --packet error signal Input: Data: in std_logic_vector(7 downto 0); --data bus Packet_Length: in std_logic_vector(11 downto 0); --packet length bus and validsignalbus Connection_Ready: in std_logic_vector; --input handshake Check_Counter: in std_logic_vector(11 downto 0); --Rcv’s counter value, for protecting from counter error Input_Port_Number: in std_logic_vector(1 downto 0); Interfaces to Data FIFO: Output: Data_Output: out std_logic_vector(7 downto 0); --prepare data for transmit side
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Interface Data_wrreq: out std_logic; --write enable to data FIFO Input: FIFO_Empty: in std_logic; --1 port in from FIFO Interfaces to Table Interface: Output: Address: out std_logic_vector(7 downto 0); --output to address FIFO Address_InputPortNumber: out std_logic_vector(1 downto 0); --expose input port number to address lookup Address_wrreq: out std_logic --write enable to address FIFO Input: Address_FIFO_Empty: in std_logic; Interfaces to Length FIFO Output: Packet_Length_Output: out std_logic_vector(10 downto 0); --expose length information to transmitter handle Length Wrreq: out std_logic;
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Function 1 Generate hand shake signal for receiver interface 2 Read data and length information from receiver FIFOs 3 Check the validation of a packet to decide either to forward it or drop it 4 Prepare address information for table interface *5 Compare the counter value with receiver side to prevent one point failure (this function is in the original code but not included in the final version)
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State Machine
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Data Flow Chart
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Simulation Results A Valid Pkt Forward Addr, 12 Bytes Finish Reading one Pkt
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An Invalid Pkt No Output to length and data FIFO Finish Dropping
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Wenzhong Wu Interfaces Switch Fabric Receive Side (Receive Handler) with Table Interfaces Table with Internal FIFOs for Switch Fabric Transmit Side
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SF_table_interface data path
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SF_Table_interface simulation result
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Simulation result of “SF_table_interface” + “switchmanagement”
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Consists of ◦ Comp 1 (Jacob Cox) ◦ Comp 2 (Jacob Cox) ◦ Comp 3 (Jacob Cox) ◦ … ◦ Transmit Port Monitor (Bryan Fleming)
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11.. 0 1212 8 3 SF_fifo2xmt_interf ace ODL_empty[ 2] ODL_empty[ 1] ODL_empty[ 0] Clk xmt_dwtreq xmt_lwtreq i_O_FIFO rd_D_FIF O i_O_FIFOi_L_FIFO xmt_wordsuse d i_D_FIFOo_D_xmt i_L_FIFOo_L_xmt reset TRANSMIT PORTSTRANSMIT PORTS 1212 8
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SF_fifo2xmt_interf ace ODL_empty[ 2] ODL_empty[ 1] ODL_empty[ 0] Clk xmt_dwtreq xmt_lwtreq i_O_FIFO rd_D_FIF O i_O_FIFOi_L_FIFO xmt_wordsuse d i_D_FIFOo_D_xmt i_L_FIFOo_L_xmt reset XMT Data Fifo(0) XMT Length Fifo(0) XMT Length Fifo(1) XMT Length Fifo(2) XMT Length Fifo(3) XMT Data Fifo(3) XMT Data Fifo(2) XMT Data Fifo(1) 1212 8
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Data Write Request Drop Packets Final Data Packet Write Length
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Data Enters Data_FIFO 1000 0010 Write Requests to the Transmit FIFOs Number of words already in the Transmit FIFO
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SF_fifo2xmt_interfac e Clk xmt_dwtreq xmt_lwtreq i_O_FIFO xmt_wordsuse d i_D_FIFOo_D_xmt i_L_FIFO o_L_xmt reset rd_D_FIF O rd_O_FIF O rd_L_FIFO SF_FIFO_monitor ODL_empty[2.. 0] Clk xfer_D_req Send_L i_O_FIFO o_read_ D o_read_L i_L_FIFO xfer_L_re q reset o_read_ O o_L_FIFO 8 CounterC i_count [11-0] Clk o_Snd_L i_read_L reset o_count[11- 0] ODL_empty[ 2] ODL_empty[ 1] ODL_empty[ 0] 1212 & xmt_port_moni tor Clk reset SF_PacketComin g xmt_wordsus ed 1212 SF_PacketLeng th SF_PacketFinish ed SF_dwtre q SF_lwtreq xmt_lwtre q xmt_dwtr eq counter_fifo_monitor_merg er
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Merger of FIFO_Monitor, Counter, and Port_Monitors results in successful initiation, countdown, and termination of data transfer. Fifo Empty Signals
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CounterC o_count[11- 0] i_count [11- 0] “x000” Clk o_Snd_L s_snd_L <= '0‘ s_en <=’0’ reset = ‘0' i_read_L = ‘1‘ & reset =‘0’ F s_snd_L <= '0‘ s_en <=’1’ T T F s_count =i_count- 1 & reset =‘0’ T s_snd_L <= ‘1‘ s_en <=’1’ s_count = i_count s_count [11- 0] F s_snd_L reset s_en i_read_L
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ODL_FIFO = “000” Send_L = ‘1’ s_i_O_FIFO = “000 to 111” reset = ‘1’
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Idle ODL_FIFO =0000 Reset =0 F T T F Get_Length F Reset =0 T Send_Data F Reset =0 T NS_FIFO<=0000 NS_length<=x00 00 s_o_read_L<=0 s_o_read_O<=0 o_read_D<=0 xfer_D_req<=000 0 xfer_L_req<=000 0 Get_Lengt h Idle NS_FIFO<=i_O_FIFO NS_length<=i_L_FIF O s_o_read_L<=1 s_o_read_O<=1 o_read_D<=0 xfer_D_req<=0000 xfer_L_req<=0000 Send_L =0 F T s_o_read_L<=1 s_o_read_O<=1 o_read_D<=0 Send_Data xfer_D_req<=000 1 xfer__L_req<=000 1 xfer_D_req<=111 0 xfer_L_req<=1110 xfer_D_req<=001 0 xfer_L_req<=0010 xfer_D_req<=010 0 xfer_L_req<=0100 xfer_D_req<=100 0 xfer_L_req<=1000 xfer_D_req<=110 1 xfer_L_req<=1101 xfer_D_req<=111 0 xfer_L_req<=1110 xfer_D_req<=101 1 xfer_L_req<=1011 xfer_D_req<=000 0 xfer_L_req<=0000 CS_FIFO=0000 CS_FIFO=othe r ASM of FIFO_Monitor FSM
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Read Signals Asserted for Output and Length FIFOs Read Signal Asserted for Data FIFO on the next clock Write signals asserted for Transmitters All FIFOs have Data = 0 Send Length indicates a count is complete
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Write Signals Asserted two clocks after all FIFOs have data
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Output Destination Packet Length Fifo Empty Signals Fifo Read Signals Length Write Signals Terminate
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Responsible for dropping packets if transmit port queue is too full Never writes a partial packet into transmit port Designed for safety, could be further optimized
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Naming conventions can make life easier Version control is good, though it has a learning curve Other concluding thoughts…
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