1. Computer Science and Engineering Copyright by Hesham El-Rewini Advanced Computer Architecture CSE 8383 January 31 2008 Session 3

2. Computer Science and Engineering Copyright by Hesham El-Rewini Contents  Review  Reservation Table  Collision Vector  Latency Analysis  State Diagrams  MAL and its bounds  Delay Insertion  Throughput  Group Work

3. Computer Science and Engineering Copyright by Hesham El-Rewini Reservation Table nA reservation table displays the time-space flow of data through the pipeline for one function evaluation nA static pipeline is specified by a single reservation table nA dynamic pipeline may be specified by multiple reservation tables

4. Computer Science and Engineering Copyright by Hesham El-Rewini Reservation Table (Cont.) nThe number of columns in a reservation table is called the evaluation time of a given function. nThe checkmarks in a row correspond to the time instants (cycles) that a particular stage will be used. nMultiple checkmarks in a row  repeated usage of the same stage in different cycles

5. Computer Science and Engineering Copyright by Hesham El-Rewini Reservation Table (Cont.) nContiguous checkmarks  extended usage of a stage over more than one cycle nMultiple checkmarks in one column  multiple stages are used in parallel nA dynamic pipeline may allow different initiations to follow a mix of reservation table

6. Computer Science and Engineering Copyright by Hesham El-Rewini Reservation Table 1234567 AXXX BXX CXX DX

7. Computer Science and Engineering Copyright by Hesham El-Rewini Nonlinear Pipeline Design nLatency The number of clock cycles between two initiations of a pipeline nCollision Resource Conflict nForbidden Latencies Latencies that cause collisions

8. Computer Science and Engineering Copyright by Hesham El-Rewini Collision Vector C = (C m, C m-1, …, C 2, C 1 ) C i = 1 if latency i causes collision (forbidden) C i = 0 if latency i is permissible C m = 1 (always) maximum forbidden latency Maximum forbidden latency: m <= n-1 n = number of columns in reservation table

9. Computer Science and Engineering Copyright by Hesham El-Rewini Example S1 S2 S3 Y X

10. Computer Science and Engineering Copyright by Hesham El-Rewini Reservation Tables for X & Y XXX XX XXX YY Y YYY S1 S2 S3 S1 S2 S3

11. Computer Science and Engineering Copyright by Hesham El-Rewini Forbidden Latencies  X after X  X after Y  Y after X  Y after Y

12. Computer Science and Engineering Copyright by Hesham El-Rewini X after X X1X2X1X2 X1 X1X2 X1X2 X1X2 X1 S1 S2 S3 X1X2 X1X1 X2 X1 X2 S1 S2 S3 5 2

13. Computer Science and Engineering Copyright by Hesham El-Rewini X after X X1X2X1 X2 X1 X2 X1 S1 S2 S3 S1 S2 S3 4 7 X1 X2 X1 X1

14. Computer Science and Engineering Copyright by Hesham El-Rewini Collision Vector  Forbidden Latencies: 2, 4, 5, 7  Collision Vector = 1 0 1 1 0 1 0

15. Computer Science and Engineering Copyright by Hesham El-Rewini Y after Y YYY YY YY YY YY YY Y S1 S2 S3 S1 S2 S3 YY YY Y Y YYY

16. Computer Science and Engineering Copyright by Hesham El-Rewini Collision Vector  Forbidden Latencies: 2, 4  Collision Vector = 1 0 1 0

17. Computer Science and Engineering Copyright by Hesham El-Rewini Latency Analysis nThe number of cycles between two initiations is the latency between them nA latency of k  two initiations are separated by k cycles nCollision  resource conflict between two initiations nLatencies that cause collision  forbidden latencies

18. Computer Science and Engineering Copyright by Hesham El-Rewini Latency Analysis (cont.) nLatency Sequence  a sequence of permissible latencies between successive initiations nLatency Cycle  a latency sequence that repeats the same subsequence (cycle) indefinitely nLatency Sequence  1, 8 nLatencies Cycle  (1,8)  1, 8, 1, 8, 1, 8 …

19. Computer Science and Engineering Copyright by Hesham El-Rewini Latency Analysis (cont.) nAverage Latency (of a latency cycle)  sum of all latencies / number of latencies along the cycle nConstant Cycle  One latency value nObjective  Obtain the shortest average latency between initiations without causing collisions.

20. Computer Science and Engineering Copyright by Hesham El-Rewini Latency Cycle (1,8) 123456789101112131415161718192021 X1X2X1X1 X2X2 X1X1 X2X2 X3X4X3X4X3X4X5X6 X1X2X1X2X3X4X3X4X5X6 X1X2X1X2X2 X1X1 X2X2 X3X4X3X4X3X4X5 Average Latency = (1+8)/2 = 4.5

21. Computer Science and Engineering Copyright by Hesham El-Rewini Latency Cycle (6) 123456789101112131415161718192021 X1X1X1 X2X2 X1X1 X2X3X2X 3X4X3 X1 X2X2 X2X3 X4 X1 X1X1 X2X2 X2 X3 X4 Average Latency = 6

22. Computer Science and Engineering Copyright by Hesham El-Rewini Exercise – Find the collision vector 1234567 AXXX BXX CXX DX

23. Computer Science and Engineering Copyright by Hesham El-Rewini Floating Point Multiplication (Revisited)  Inputs (Mantissa 1, Exponenet 1 ), (Mantissa 2, Exponent 2 )  Add the two exponents  Exponent-out  Multiple the 2 mantissas  Normalize mantissa and adjust exponent  Round the product mantissa to a single length mantissa. You may adjust the exponent

24. Computer Science and Engineering Copyright by Hesham El-Rewini Linear Pipeline for floating-point multiplication Add Exponents Multiply Mantissa Normalize Round Partial Products Accumulator Add Exponents Normalize Round Re normalize

25. Computer Science and Engineering Copyright by Hesham El-Rewini Linear Pipeline for floating-point Addition Partial Shift Add Mantissa Subtract Exponents Find Leading 1 Round Re normalize Partial Shift

26. Computer Science and Engineering Copyright by Hesham El-Rewini Combined Adder and Multiplier Partial Shift Add Mantissa Exponents Subtract / ADD Find Leading 1 Round Re normalize Partial Shift Partial Products C A B ED F G H

27. Computer Science and Engineering Copyright by Hesham El-Rewini Reservation Table for Multiply 1234567 AX BXX CXX DXX EX F G H

28. Computer Science and Engineering Copyright by Hesham El-Rewini Reservation Table for Addition 123456789 AY B CY DY EY FYY GY HYY

29. Computer Science and Engineering Copyright by Hesham El-Rewini Mul – Mul Collision (launch after 1 cycle) 1234567 AXZ BXX ZZ CX Z DXZX EXZ F G H

30. Computer Science and Engineering Copyright by Hesham El-Rewini Mul –Mul Collision (lunch after 2 cycles) 1234567 AXZ BXXZZ CXXZZ DXX Z EX F G H

31. Computer Science and Engineering Copyright by Hesham El-Rewini Mul – Mul Collision (launch after 3 cycles) 1234567 AXZ BXXZZ CXXZZ DXX EX F G H

32. Computer Science and Engineering Copyright by Hesham El-Rewini Collision Vector for Multiply after Multiply Forbidden Latencies: 1, 2 Collision vector 0 0 0 0 1 1  11 Maximum forbidden latency = 2  m = 2

33. Computer Science and Engineering Copyright by Hesham El-Rewini Single Function Controller C.V. Gate Grant X Grant X if 0 0 OR X after X

34. Computer Science and Engineering Copyright by Hesham El-Rewini Controller for a dual-function pipeline C.V. M after M C.V. M after A Gate Grant AGrant M OR Grant M if 0 0 C.V. A after M C.V. A after A Gate Grant AGrant M OR Grant A if 0 0

35. Computer Science and Engineering Copyright by Hesham El-Rewini State Diagram nIt specifies the permissible state transitions among successive initiations nCollision vector corresponds to the initial state at time t = 1 (initial collision vector) nThe next state comes at time t + p, where p is a permissible latency in the range 1 <= p < m

36. Computer Science and Engineering Copyright by Hesham El-Rewini Right Shift Register The next state can be obtained with the help of an m-bit shift register 0 0 1 Collision Safe to allow an initiation Each 1-bit shift corresponds to increase in the latency by 1

37. Computer Science and Engineering Copyright by Hesham El-Rewini Example (Revisited) S1 S2 S3 Y X

38. Computer Science and Engineering Copyright by Hesham El-Rewini Reservation Tables for X & Y XXX XX XXX YY Y YYY S1 S2 S3 S1 S2 S3

39. Computer Science and Engineering Copyright by Hesham El-Rewini Collision Vector  Forbidden Latencies: 2, 4, 5, 7  Collision Vector = 1 0 1 1 0 1 0

40. Computer Science and Engineering Copyright by Hesham El-Rewini The next state nThe next state is obtained by bitwise ORing the initial collision vector with the shifted register nC.V. = 1 0 1 1 0 1 0 (first state) 0 1 0 1 1 0 1 C.V. 1-bit right shifted 1 0 1 1 0 1 0 initial C.V. ---------------- OR 1 1 1 1 1 1 1

41. Computer Science and Engineering Copyright by Hesham El-Rewini State Diagram for X after X 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 3 6 8+8+ 6 8+8+ 8+8+ 3*3* 1*1*

42. Computer Science and Engineering Copyright by Hesham El-Rewini Cycles nSimple cycles  each state appears only once (3), (6), (8), (1, 8), (3, 8), and (6,8) nGreedy Cycles  simple cycles whose edges are all made with minimum latencies from their respective starting states (1,8), (3)  one of them is MAL

43. Computer Science and Engineering Copyright by Hesham El-Rewini MAL nMinimum Average latency nAt least one of the greedy cycles will lead to the MAL nConsider state diagram for Y, MAL is 3 (See diagram)

44. Computer Science and Engineering Copyright by Hesham El-Rewini Collision Vector  Forbidden Latencies: 2, 4  Collision Vector = 1 0 1 0

45. Computer Science and Engineering Copyright by Hesham El-Rewini State Diagram for Y after Y 1 0 1 1 1 0 1 1 0 1 1 3 5+5+ 5+5+ 5+5+ 3*3* 1*1*

46. Computer Science and Engineering Copyright by Hesham El-Rewini Bounds on the MAL nMAL is lower bounded by the maximum number of checkmarks in any row of the reservation table. (Shar, 1972) nMAL is lower than or equal to the average latency of any greedy cycle in the state diagram. (Shar, 1972) nThe average latency of any greedy cycle is upper- bounded by the number of 1’s in the initial collision vector plus 1. This is also an upper bund on the MAL. (Shar, 1972)

47. Computer Science and Engineering Copyright by Hesham El-Rewini Delay Insertion nThe purpose is to modify the reservation table, yielding a new collision vector nThis may lead to a modified state diagram, which may produce greedy cycles meeting the lower bound on MAL

48. Computer Science and Engineering Copyright by Hesham El-Rewini Example S1 S2 S3 output

49. Computer Science and Engineering Copyright by Hesham El-Rewini Example (Cont.) 12345 S1XX S2XX S3XX Forbidden Latencies: 1, 2, 4 C.V.  1 0 1 1

50. Computer Science and Engineering Copyright by Hesham El-Rewini Example (Cont.) State Diagram 1 0 1 1 3* 5+ MAL = 3

51. Computer Science and Engineering Copyright by Hesham El-Rewini Example (Cont.) S1 S2 S3 output D1 D2

52. Computer Science and Engineering Copyright by Hesham El-Rewini Example (Cont.) 1234567 S1XX S2XX S3XX D1X D2X Forbidden: 2, 6 C.V.  1 0 0 0 1 0

53. Computer Science and Engineering Copyright by Hesham El-Rewini Group Activity 1 Find the State Diagram

54. Computer Science and Engineering Copyright by Hesham El-Rewini Pipeline Throughput nThe average number of task initiations per clock cycle nThe inverse of MAL

55. Computer Science and Engineering Copyright by Hesham El-Rewini Group Activity 2 1234 S1XX S2X S3X C.V State DiagramSimple Cycles Greedy Cycles MAL Throughput (t = 20 ns)