1. Digital networks classification Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu www.testgroup.polito.it Lecture 4.1

2. 2 4.1 Goal  This lecture introduces a taxonomy on digital networks, focusing, in particular, on:  Combinational vs. sequential  Mealy vs. Moore  I/O clustering.

3. 3 4.1 Prerequisites  Module 3

4. 4 4.1 Homework  No particular homework is foreseen

5. 5 4.1 Further readings  No particular suggestion

6. 6 4.1 Outline  Combinational vs. sequential networks  Moore vs. Mealy machines  I/O clustering.

7. 7 4.1 Some graphic conventions Hereinafter: will identify a bus or a set of wires will identify a single bit wire

8. 8 4.1 Digital network A proper assembly of electronic devices, designed to store, transform, and communicate information in digital form

9. 9 4.1 Digital networks

10. 10 4.1 Digital networks

11. 11 4.1 Digital networks Primary Inputs (PIs) Primary Outputs (POs)

12. 12 4.1 Digital networks Digital networks are usually classified as: combinationalcombinational sequentialsequential

13. 13 4.1 A digital network is combinational iff its POs are completely determined by its present PIs, only. Combinational network

14. 14 4.1 A digital network is combinational iff its netlist doesn’t contain any feedback loop. Combinational network

15. 15 4.1 A digital network is sequential if its POs are a function of past as well as present values of the PIs. Sequential network

16. 16 4.1 A digital network is sequential if its netlist contains one, or more, feedback loops. Sequential network 1

17. 17 4.1 An example S R

18. 18 4.1 An example S R S R Feedback

19. 19 4.1 The concept of state A sequential circuit must be able to “remember”, or “store”, some information items related to the values the PIs have got. Such a storing capability is accomplished in terms of “internal states”: in any instant, the circuits is in a well defined “state”, univocally represented by the values got by the set of “internal state variables”.

20. 20 4.1 General structure of a sequential network Combinational network PIs POs Feedback elements

21. 21 4.1 General structure of a sequential network Combinational network PIs POs Feedback elements They act as state variables and their values determine the “state” of the network.

22. 22 4.1 General structure of a sequential network Combinational network PIs POs Feedback elements Present-state variables or Secondary Inputs

23. 23 4.1 General structure of a sequential network Combinational network PIs POs Feedback elements Next-state variables or Secondary Outputs

24. 24 4.1 State variables  A sequential network has as many state variables as feedback elements  A network with n state variables is characterized by 2 n possible states.

25. 25 4.1 Sequential network classification Combinational network PIs POs Feedback elements

26. 26 4.1 Sequential network classification Combinational network PIs POs Feedback elements According to the “feedback elements” nature, sequential networks are classified as: asynchronousasynchronous synchronoussynchronous

27. 27 4.1 Asynchronous networks  Each feedback element is just a wire. synchronized  The information flow through feedback elements is a continuum and not synchronized by any external event.

28. 28 4.1 Asynchronous network structure Combinational network PIs POs

29. 29 4.1 Asynchronous network structure Combinational network PIs POs Present-state variables Next-state variables

30. 30 4.1 Synchronous networks  Each feedback is always performed via a particular device, named Flip-Flop.  Flip-Flop behavior is controlled and timed by an ad-hoc signal, usually referred to as clock.  The information flow through the feedback elements is thus “synchronized” by the clock.

31. 31 4.1 D Q CLK Flip-Flop behavior

32. 32 4.1 CLK D Q Clock Flip-Flop behavior

33. 33 4.1 CLK D D Q Clock Input Flip-Flop behavior

34. 34 4.1 CLK D Q D Q Clock Input Output Flip-Flop behavior

35. 35 4.1 State register The set of Flip-Flops is often referred to as “State Register”, since it stores the network state variables.

36. 36 4.1 Synchronous network structure Combinational network PIs POs State register CLK

37. 37 4.1 Finite State Machines Finite State Machines Synchronous networks, being characterized by a finite # of flip-flops, and thus of states, are very often referred to as Finite State Machines (FSMs).

38. 38 4.1 Reset signal & Reset state Any FSM, regardless its complexity, must have:  a particular control input signal, named reset signal (or simply reset) characterized by the highest priority  a particular state, named reset state, in which the network moves whenever the reset signal is asserted.

39. 39 4.1 Asynchronous reset Combinational network PIs POs State register CLKreset

40. 40 4.1 Outline  Combinational vs. sequential networks  Moore vs. Mealy machines  I/O clustering.

41. 41 4.1 Combinational network splitting Combinational network PIs POs State register CLKreset

42. 42 4.1 Combinational network splitting Combinational network PIs POs State register CLKreset Can be split in two independent networks

43. 43 4.1 Next state network State register CLK Primary Output network reset PIsPOs

44. 44 4.1 Next state network State register CLK Primary Output network The structure of this network allows us to distinguish between: Moore machinesMoore machines Mealy machinesMealy machines reset PIsPOs

45. 45 4.1 Moore machines  POs depend on the present state value, only. POs can change only when state changes.

46. 46 4.1 Next state network State register PIsPOs CLK Primary Output network reset

47. 47 4.1 Mealy machines  POs depend on both the present state value and the PIs values. POs can change not only when the state changes, but when PIs change, too.

48. 48 4.1 PI PO CLKRESET Next state network State register Primary Output network

49. 49 4.1 Outline  Combinational vs. sequential networks  Moore vs. Mealy machines  I/O clustering.

50. 50 4.1 Digital networks I/O clustering  I/O pins of digital networks are usually clustered in 3 main categories:  Data I/Os  Clock I/Os  Control I/Os.

51. 51 4.1 Digital networks I/O clustering

52. 52 4.1 Data I/Os Data Inputs Data Outputs

53. 53 4.1 Clock I/Os Clock Inputs

54. 54 4.1 Clock I/Os Clock Inputs They synchronize the overall behavior of the network by: sampling data and control inputs updating data and control outputs

55. 55 4.1 Edge vs. pulse triggering Sampling and updating can be triggered by clock’s  raising or falling edges  positive or negative pulses.

56. 56 4.1 Edge triggering behavior The same clock edge samples the inputs and concurrently updates the outputs:  raising edge  positive edge triggered  falling edge  negative edge triggered.

57. 57 4.1 Positive edge triggered sample & update

58. 58 4.1 Clock D Q Positive edge triggered

59. 59 4.1 Clock D Q Positive edge triggered

60. 60 4.1 Clock D Q Positive edge triggered

61. 61 4.1 Clock D Q Positive edge triggered

62. 62 4.1 Negative edge triggered sample & update

63. 63 4.1 Negative edge triggered

64. 64 4.1 Clock D Q Negative edge triggered

65. 65 4.1 Clock D Q Negative edge triggered

66. 66 4.1 Clock D Q Negative edge triggered

67. 67 4.1 Pulse triggering behavior An edge of the clock samples the inputs values and the other edge updates the outputs.

68. 68 4.1 Positive pulse triggered

69. 69 4.1 Positive pulse triggered sample

70. 70 4.1 Positive pulse triggered update

71. 71 4.1 Positive pulse triggered

72. 72 4.1 Positive pulse triggered

73. 73 4.1 D Q Positive pulse triggered CLK

74. 74 4.1 D Q Positive pulse triggered CLK

75. 75 4.1 D Q Positive pulse triggered CLK

76. 76 4.1 Graphical notation Clock inputs are usually identify as follows: Clock Inputs

77. 77 4.1 Control I/Os Control Inputs Control Outputs

78. 78 4.1 Control I/Os Control Inputs Control Outputs They control the behavior of the network, by stating the operations to be performed.

79. 79 4.1 Control Inputs classification According to their asserting characteristics, Control Inputs are usually classified as:  Synchronous  Asynchronous.

80. 80 4.1 Control Inputs classification According to their asserting characteristics, Control Inputs are usually classified as:  Synchronous  Asynchronous. When asserted, they become active at the next clock (edge or pulse), only

81. 81 4.1 Reset Clock Synchronous reset

82. 82 4.1 Reset Q Clock Synchronous reset

83. 83 4.1 Clock D Enable Q

84. 84 4.1 Control Inputs classification According to their asserting characteristics, Control Inputs are usually classified as:  Synchronous  Asynchronous. When asserted, they are immediately active, regardless the clock.

85. 85 4.1 Clock Reset Asynchronous reset

86. 86 4.1 Clock Reset Q Asynchronous reset

87. 87 4.1