1. Flip-Flops and Registers
Chapter 10
Flip-Flops and Registers 1

2. Objectives You should be able to:
Explain the internal circuit operation of S-R and gated S-R flip-flops.
Compare the operation of D latches and D flip-flops by using timing diagrams.
Describe the difference between pulse-triggered and edge-triggered flip-flops. 2

3. Objectives (Continued)
Explain the theory of operation of master-slave devices.
Connect IC J-K flip-flops as toggle and D flip-flops.
Use timing diagrams to illustrate the synchronous and asynchronous operation of J-K flip-flops.
Use VHDL to design flip-flops for CPLD implementation. 3

4. S-R Flip-Flop Data storage circuit Cross-coupled NOR scheme
Asynchronous set and reset 4

5. S-R Flip-Flop
Function table 5

6. S-R Flip-Flop
Cross-coupled NAND scheme 6

7. S-R Flip-Flop
Function table 7

8. S-R Flip-Flop Both true and complemented Q outputs
Symbols for a S-R FF 8

9. S-R Flip-Flop Timing Analysis9

10. S-R Flip-Flop Application
Storage register to remember time of day when a temperature limit switch goes high. 11

11. Gated S-R Flip-Flop
Asynchronous – output responds immediately to input
Synchronous – output responds in step with a control input 13

12. Gated S-R Flip-Flop
Function table and symbol 14

13. Gated D Flip-Flop
Data flip-flop with example inputs and outputs 15

14. Discussion Point
How will the complement of an output differ from the output?
Explain the difference between synchronous and asynchronous inputs. 16

15. D Latch: 7475 IC; VHDL Description
Four transparent D latches
Logic symbol and pin configuration 17

16. D Latch: 7475 IC;
Function table shows that Q output follows D (transparent) if enable line is HIGH.
When E is low, Q is latched to prior value of D. 17

17. VHDL Description of a D Latch
Block design file

18. VHDL Description of a D Latch
VHDL design file

19. VHDL Description of a D Latch
Simulation file

20. D Flip-Flop: 7474 IC VHDL Description
Positive edge-triggered device
Transitions of output occur at the rising edge of input trigger pulse
Clock signal usually used as trigger pulse instead of an enable line 19

21. 7474 Integrated Circuit D Flip-Flop
Logic symbol and pin configuration 20

22. Integrated Circuit D Flip-Flop
Positive edge-detection circuit 21

23. Integrated Circuit D Flip-Flop
Synchronous inputs
D (Data)
Cp (Clock)
Asynchronous inputs
SD (Set)
RD (Reset)
Setup Time
D must be stable before transition of Cp 22

24. Integrated Circuit D Flip-Flop22

25. VHDL Description of a D Flip-Flop
Block design file 22

26. VHDL Description of a D Flip-Flop
Listing file 22

27. VHDL Description of a D Flip-Flop
Flow chart 22

28. VHDL Description of a D Flip-Flop
Simulation file 22

29. Master-Slave J-K Flip-Flop
Toggle mode
Switches to opposite state at active clock edge
Master-slave
Master receives data while input trigger is HIGH
Slave receives data from master and outputs it when clock goes LOW 24

30. Master-Slave J-K Flip-Flop
Function Table 25

31. Master-Slave J-K Flip-Flop
Equivalent circuit and logic symbol 26

32. Master-Slave J-K Flip-Flop
Enable/disable operation of the CP line 27

33. Master-Slave J-K Flip-Flop
Pulse-triggered (level-triggered)
Input data are read during entire time clock pulse is at a HIGH level
Noise can appear on J and K while CP is high
Called “Ones catching”
Eliminated by newer designs using edge triggering 27

34. Edge-Triggered J-K Flip-Flop
Accepts data on the J and K inputs only at the active clock edge
Symbols for positive and negative edge triggered J-K FFs 28

35. Edge-Triggered J-K Flip-Flop
Function Table 29

36. VHDL Description of an Edge-Triggered J-K Flip-Flop
Block design file 29

37. VHDL Description of an Edge-Triggered J-K Flip-Flop
VHDL design file 29

38. VHDL Description of an Edge-Triggered J-K Flip-Flop
Flowchart 29

39. VHDL Description of an Edge-Triggered J-K Flip-Flop
Simulation file 29

40. Discussion Point
How are pulse triggered (level triggered) devices different from edge triggered devices?
What is ones catching?
Identify the synchronous and asynchronous inputs on a JK flip-flop logic symbol 30

41. Integrated Circuit J-K Flip-Flop
7476 – positive pulse-triggered
74LS76 - negative edge-triggered
Logic symbol and pin configuration 31

42. Integrated Circuit J-K Flip-Flop31

43. Integrated Circuit J-K Flip-Flop
To form a D flip-flop add an inverter 33

44. Integrated Circuit J-K Flip-Flop
To form a toggle flip-flop tie inputs HIGH 34

45. Using an Octal D Flip-Flop in a Microcontroller Application
Octal ICs - eight on a chip
8-bit register
74HCT273 logic diagram 35

46. Using an Octal D Flip-Flop in a Microcontroller Application
The 74HCT273 as an update and hold register
Figure 10-45 36

47. Altera’s LPM Flip-Flop
Quartus II provides a general-purpose flip-flop called LPM_F
Found in Library of Parameterized Modules subdirectory /megafunctions/storage
Can be used to implement several types of flip-flops

48. Altera’s LPM Flip-Flop
LPM D flip-flop block design file

49. Altera’s LPM Flip-Flop
LPM D flip-flop simulation file

50. Altera’s LPM Flip-Flop
LPM octal D flip-flop block design file

51. Altera’s LPM Flip-Flop
LPM octal D flip-flop simulation file

52. Summary
The S-R flip-flop is a single-bit data storage circuit that can be constructed using basic gates.
Adding gate enable circuitry to the S-R flip-flop makes it synchronous. This means that it will operate only under the control of a clock or enable signal. 37

53. Summary
The D flip-flop operates similar to the S-R, except it has only a single data input, D.
The 7475 is an integrated-circuit D latch. The output (Q) follows D while the enable (E) is HIGH. When E goes LOW, Q remains latched. 38

54. Summary
The 7474 is an integrated-circuit D flip-flop. It has two synchronous inputs, D and Cp, and two asynchronous inputs, SD and RD. Q changes to the level of D at the positive edge of Cp. Q responds immediately to the asynchronous inputs regardless of the synchronous operations. 39

55. Summary
The J-K flip-flop differs from the S-R flip-flop because it can also perform a toggle operation. Toggling means that Q flips to its opposite state.
The master-slave J-K slip-flop consists of two latches: a master that receives data while the clock trigger is HIGH, and a slave that receives data from the master and outputs it to Q when the clock goes LOW. 40

56. Summary
The 74LS76 is an edge-triggered J-K flip-flop IC. It has synchronous and asynchronous inputs. The 7476 is similar, except it is a pulse-triggered master-slave type.
The 74HCT273 is an example of an octal D flip-flop. It has eight D flip-flops in a single IC package, making it ideal for microprocessor applications. 41

57. Summary
The Quartus II software provides a general-purpose flip-flop in the LPM subdirectory that can be used to implement multi-bit D and toggle flip-flops. 41