1. Interrupt Interrupt – to break the flow of speech or action of (someone) by saying or doing something (Longman dictionary)

2. Examples When your phone rings during a lecture, what will happen? When you are studying then your cell phone rings – what will you do? –When you finish talking on the phone then you will continue with your study Now your phone rings again and someone also knocking at your door then what will you do? When being interrupted, you will perform some pre- defined action Interrupt has priority – some interrupt is more important than the others. For example, answering your phone is more important than opening the door

3. Interrupts Interrrupt is a procedure that interrupts whatever program is currently executing by the CPU. Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data-transfer rates, eg a keyboard. During an interrupt, the CPU will perform pre-defined operations according to the interrupt nature so the microprocessor can execute other software before the interrupt occurs

4. Interrupt Once the CPU is interrupted then it will perform the pre-defined operation according to the interrupt nature

5. Use of interrupt How to get key typed in the keyboard or a keypad? Polling The CPU executes a program that check for the available of data If a key is pressed then read the data, otherwise keep waiting or looping!!! Just like the mechanism used in LAB for sensing the keypad Interrupt The CPU executes other program, as soon as a key is pressed, the Keyboard generates an interrupt. The CPU will response to the interrupt – read the data. After that returns to the original program. So by proper use of interrupt, the CPU can serve many devices at the “same time” from the user’s point of view

6. Polling Vs Interrupt No key pressed Do key pressed action Polling Doing Something else interrupt Response To interrupt Return To original program

7. Example of interrupt How to control a robot that has sensors to detect obstacles and makes a turn to avoid the obstacle Polling –Move forward in a pre-defined unit –Check sensor reading –Do nothing if no obstacle or turn if obstacle detected –Loop back and move forward again sensor

8. Interrupt Controlling a robot by interrupt –Keeping moving until interrupted by the sensor –Interrupt received then do pre-defined operation –After finishing the interrupt service return to normal operation ie keep moving forward again

9. Polling Vs Interrupt Control of a robot Move forward Check sensor Y Stop or turn Move forward interrupt

10. Interrupt Vs Polling Which mechanism is better to controlling the robot if your objective is to move from point A to point B in the shortest time –Why??????

11. Introduction Interrupt can be caused by an external device or an internal event When interrupt occurs, program control is transferred from the original program to the Interrupt Service Routine (ISR) The mechanism is similar to a subroutine call. The CPU remembers the location where it left off in the original program and then executes the interrupt service routine. After this routine has run to completion, program control is returned to the point where the CPU originally was executing.

12. Program flow with interrupt Interrupt service routine ISR Original Program Interrupt occurs Return to the original Program IRET

13. Introduction to interrupt 8086 can implement 256 different types of interrupts The interrupts are divided into 5 groups Five groups: external hardware interrupt, software interrupts, internal interrupts, nonmaskable interrupt, and reset The interrupt routines for external hardware, software, and nonmaskable interrupts can be defined by user (you can write your own ISR)

14. Introduction to interrupt When more than one interrupt occur then priorities of the interrupts are compared in order to determine which interrupt to serve first (open the door or answer the phone?)

15. Interrupt Priority Hardware, software, and internal interrupts are serviced on a priority basis Priority hierarchy groups: internal interrupt, nonmaskable interrupt, software interrupt, and external hardware interrupt Internal interrupt group has the highest priority External hardware interrupt group has the lowest priority Within a group, different interrupts have different priority levels represented by the type number (or interrupt number)

16. Interrupt priority Interrupt typePriority level InternalHighest Non-maskableVery high softwareHigh External (32 – 255) low

17. Interrupt priority Type 0 – highest priority Type 255 – lowest priority Example – an internal interrupt, divide error, is a type 0 interrupt Divide error : divide by zero Overflow is type 4 When a CPU is performing an interrupt service routine, it can be interrupted by a higher priority interrupt. If a lower priority occurs, the newly occurred interrupt must wait

18. Multiple interrupt Interrupt Interrupt by Higher priority

19. Interrupt address pointer table When an interrupt occurs, CPU will perform some routine (function) How to locate the appropriate function or where is the function stored in memory???? In 8086, the interrupt address pointer table is serving as a link between the interrupt numbers to the locations of their service routines in memory

20. Function of interrupt pointer table Interrupt Address Pointer Table Interrupt Number Address (CS+IP) of Interrupt Service Routine

21. Interrupt Pointer Table For 8086 the table is stored in memory location (address) 00H – 3FFH (1K) Address pointers identify the starting locations (address) of their service routines in program memory. For the 8086, each pointer requires two words (4 bytes: segment + offset) The higher address word is the base address and will be loaded into the CS register The lower address word is the offset address and loaded into the IP register

22. Function of the pointer table Pointer table Interrupt Number/vector Address of Service routine CS + IP

23. Interrupt address table Vector 0 = interrupt type 0

24. Example If INT50 occurs what are the addresses storing information for CS50 and IP50? CS50 = Code segment value for ISR of interrupt 50 This represent the interrupt level 50 Starting from 0 type 50 should be in 50x4 since each pointer requires 4 bytes In HEX, 200 is C8H to CBH (4 bytes) C8 stores the IP value, CA stores the CS

25. Interrupt pointer table Memory FFFFFH 00-3FFHInterrupt pointer table Interrupt No. 200 ISR for INT 200 AABBCH CS AABBH IP 000CH

26. Interrupt in ADuC832 In ADuC832 The location for the ISR is fixed For example: The ISR for External Interrupt 0 (IE0) must be stored in memory location 0003H So the directive ORG is used to put the ISR to the proper address Example ORG 0003H ISR_IE0: … RETI

27. Interrupt instructions MnemonicMeaningFormatOperationFlags affected CLIClear interrupt flag CLIIF = 0IF STISet interrupt flag STIIF =1IF INT nType n software interrupt INT nTF, IF IRETInterrupt return IRETALL

28. Interrupt instructions MnemonicMeaning Format OperationFlags affected INTOInterrupt on overflow INTOINT 4 if O = 1 TF, IF TF – trap flage HLTHaltHLTWait for an external interrupt or reset to occur None WAITWaitWAITWait for /test input to go active None

29. Interrupt instruction INT 80 – allows you to execute the Interrupt service routine for interrupt 80 in your program Similar to a subroutine call but calling an ISR

30. Interrupt request input (INTR) How can an external device interrupt the CPU? The CPU has an input(s) pin for accepting the interrupt request signal For 8086, this input pin is called INTR (interrupt request)

31. The Interrupt Flag If the interrupt flag (IF) is set (=1) then external hardware can initiate an interrupt via the INTR input of the microprocessor If IF flag is clear (=0) then the external device cannot initiate an interrupt During the initiation sequence of an interrupt service routine, the 8086 automatically clears IF. This masks out (disable) the occurrence of any additional external hardware interrupt. The IF flag should be re-enable at the end of the service routine

32. External hardware interrupt interface An interrupt interface circuit is required to drive the INTR (Interrupt Request) input of the 8086 (WHY????) There is only 1 interrupt input in the 8086 The circuit will support external interrupt 32 to 255 The circuit must identify which of the pending active interrupt has the highest priority and then pass its type number to the 8086 The 8086 samples the INTR input during the last clock period of each instruction execution cycle

33. Interrupt interface circuit Interface circuit AD0-AD7 8086 CPU INTR INTA External Hardware interrupt

34. External hardware interrupt INTR =1 implies an active interrupt request INTR is level-sensitive must be held at ‘1’ until it is recognized INTR signal must be clear before the service routine runs to completion; otherwise, the same interrupt may be acknowledged again

35. Interrupt sequences INTA – interrupt acknowledge is used to inform the recognition of an interrupt Two pulses are produced at INTA during the interrupt acknowledge bus cycle The first pulse signals external circuit that the interrupt request has been acknowledged and to prepare to send the interrupt type number (or just the interrupt number) The second pulse tells the external circuit to put the type number on the data bus The type number is put on the bit 0 to 7 of the address/data bus

36. External Interrupt sequence The interrupt sequence begins when an external device requests service by activating one of the interrupt inputs (32 to 255) External circuit evaluates the priority of the input If there is no interrupt already in progress and this interrupt is of higher priority than any other interrupt that is simultaneously active, the external circuit must issue a request for service to the 8086 INTR switches to 1

37. Interrupt sequences 8086 checks the setting of the IF (interrupt flag) If IF is 0 then no interrupt action will be performed If IF is 1 then external hardware interrupts are enabled and the service routine is to be initiated Interrupt acknowledge cycle is initiated T1 of the first bus cycle, address/data is put in the high- Z state and stays in this state for the rest of the cycle During T2 and T3, /INTA (active-low) is switched to 0. And the INTR can be removed

38. Interrupt sequences In the second interrupt acknowledge bus cycle, the INTA tells the external circuit to put the type number of the active interrupt on the data bus External circuit put the type number on the data bus. This must be valid during T3 and T4 DT/R, /DEN, and M/IO must set properly to read the type number from the data bus After reading the type number, the interrupt acknowledge part of the interrupt sequence is completed

39. Interrupt acknowledge bus cycles Note: /INTA is issued twice

40. Interrupt sequences After reading the type number, the corresponding interrupt service routine (ISR) is executed Flag register is saved in the stack IF is clear to disable other hardware interrupt TF is clear to disable single-step mode if it is active Current values of CS and IP are saved in the stack

41. Interrupt sequence The type number is internally multiplied by 4, and the result is used as the address of the first word of the interrupt vector in the pointer table Service routine is initiated IRET at the end of the service routine causes the old contents CS and IP to be restored

42. Pay attention to the INTR

43. Ack Interrupt Read Interrupt type Call ISR Return to interrupted program Before Acknowledge The IF flag must be 1 Type number is input at the 2 nd INTA cycle Address of ISR is obtained by x4 the Interrupt type number and address the Interrupt pointer Table IRET is reached

44. Interrupt service routine template PUSH XX PUSH YY PUSH ZZ POP ZZ POP YY POP XX IRET To save registers and parameters on the stack Main body of the service routine To restore registers and parameters from the stack Return to main program

45. Interrupt interface 8086 INTR External devices Interrupt interface

46. Expanding interrupt input Can accept 7 inputs the /IRX input is used for supplying the Type No Priority is Resolve by storing The ISR at the Proper location A buffer/latch

47. Interrupt interface requirements Support a many-to-one configuration Able to issue the INTR signal Able to supply the interrupt number to the CPU Able to resolve priority issue

48. Interrupt interface using the NAND gate The diagram in the previous page shows how to implement an interrupt interface using a simple NAND gate and a latch The number of interrupt that can be supported is 7 !!!! (D7 is always a ‘1’) The interrupt type number is derived from the active interrupt input For example, if IR0 is active then the interrupt type number is 11111110 For example, if IR1 is active then the interrupt type number is 11111101 Using the previous circuit, can you handle two interrupts activated at the same time ?????

49. Resolving Priority issue When two IRs (interrupt requests) active at the same time then we must serve the one with higher priority first –execute the ISR for higher priority interrupt With the NAND gate and latch setup, we need to manipulate the interrupt pointer table

50. Resolving priority issue If IR0 has a higher priority and if IR0 and IR1 active at the same time then the Interrupt type number received by the CPU is 11111100 (FCH) CPU will go to location = FCH x 4 of the interrupt pointer table to look for the ISR If we put the address of ISR for IR0 in that location then ISR of IR0 will be executed and implying that IR0 has a higher priority!

51. Interrupt pointer table Only IR0 active IR5 and IR0 active Interrupt Number Address in HEX Content FEH 1111 1110 3FACDH 3F8ABH DEH 1101 1110 37ACDH 378ABH Determine another address with the content CDABH

52. Self test What are needed in order to accomplish an interrupt mechanism? Can the circuit in the previous page support all the features? –Can it activate the INTR? –Can it produce the interrupt type number? –Can it resolve priority issue?

53. Software interrupt 256 software interrupts (0 to 255) Usage INT n, n is the interrupt type number During software interrupt, no external interrupt acknowledge bus cycles are initiated Control is passed to the start of the service routine immediately upon completion of execution of the interrupt instruction Software interrupts have a higher priority than external interrupts and cannot be masked out by IF

54. Nonmaskable interrupt (NMI) NMI is another input pin in the 8086 to support nonmaskable interrupt. The other interrupt input is INTR NMI is also initiated from external hardware It cannot be masked out with the IF flag NMI interrupt will send a 1 to the NMI input of the 8086 NMI is positive edge triggered (low to high) NMI signal must be active for 2 consecutive clock cycles. Or must remain a ‘1’ until it is recognized by the microprocessor.

55. NMI NMI causes the current flags, current CS, and current IP to be pushed onto the stack Interrupt enable flag (IF) is cleared to disable all external hardware interrupts Single-step mode of operation is disable NMI is type 2 interrupt with a very high priority NMI is for hardware events that must be responded to immediately (major system faults), eg detection of power failure and detection of a memory read error

57. 8259A Interrupt controller Instead of using a NAND gate and a latch, the interrupt mechanism is usually implemented with a more advanced digital device – Interrupt controller 8259A is a typical example 8259A is a hardware device to support the interrupt mechanism It can support up to 8 vectored priority encoded interrupts to the microprocessor Can be expanded (using more 8259) to accept up to 64 interrupt requests using master/slaves configuration

58. 8259A programmable interrupt controller 8259A is programmed via the microprocessor through the host processor interface The host interface consists of: data bus, read, write, interrupt request (INT), interrupt acknowledge (INTR) and chip select The data can be command words, status information, or interrupt type numbers. The INT and INTR are connected to the microprocessor. They are used for handshaking

59. Pins assignment for 8259A Interrupt input from external devices Comm. with CPU Control signals Cascade for multiple 8259A setup

60. Interrupt controller INT generated by 8259 is connected to INTR of 8086 INT =1 when 8259 receives a valid interrupt request INTA produced by the microprocessor consists of two pulse and it signals the 8259 to put the interrupt type number on the data bus

61. Interfacing the 8259A to 8086 From the CPU’s point of View, the 8259 is also a I/O device!!!! How the 8259 is enabled? Cascading Using master Slave connection This is a PAL

62. Block Diagram of 8259A

63. Interrupt mask register Interrupt mask register (IMR) can be used to enable or mask out individually the interrupt request inputs There are 8 bits and each bit represents one interrupt input 0- enable; 1- mask out (disable) The register can be read from or written into under software control (programmed via the microprocessor

64. Interrupt request register (IRR) IRR stores the current status of the interrupt request inputs Has one bit for each IR input The values in the bit positions reflect whether the interrupt inputs are active or inactive

65. Priority resolver The priority resolver identifies which of the active interrupt inputs has the highest priority The resolver can be configured to work using a number of different priority schemes through software It will signal the control logic that an interrupt is active and in response, the control logic causes the INT signal to be issued

66. 8259 interrupt controller The in-service register (ISR) stores the interrupt level that is presently being serviced. During the first INTA pulse in an interrupt acknowledge bus cycle, the level of the highest active interrupt is strobed into ISR. The ISR cannot be written into by the microprocessor but its contents may be read as status The cascade buffer/comparator section provides the interface between master and slave 8259As. This permits easy expansion of the interrupt interface using a master/slave configuration

67. Connecting two 8259A

68. Master/slave SP/EN – 1 (master); 0 (slave)

69. Summary Using interrupt allows CPU to serve many devices at the same time Different types – software, hardware Interrupt – has priority. Always serve the high priority first ISR – interrupt service routine tells the CPU what to do during an interrupt A table stores the locations (represented by the corresponding CS and IP values) of the ISRs

70. Summary INTR, NMI are inputs for external interrupt INTA – output to acknowledge the interrupt and ask for the interrupt vector Interrupt controller is to expand the interrupt interface, resolve priority etc