1. WP4 Progress Photonic Systems Group

2. 2Tyndall, Photonic Systems Group 3-Gate pattern recognition system SOA1 SOA2 Repeated data 10-40Gb/s Target pattern 2 4 1 Output Push Pull 1 Clock SOA1 SOA2 SOA1 SOA2 delay 3 1 3 Initialise Probe with reset Regenerated Loop length (n+1)T Data XOR Target A B C ( ( n n + + 1 1 ) ) T T XOR O O R R A A N N D D n T Target pattern Data 10-40Gb/s Initialise Optical circuit outline Equivalent logic circuit Last meeting: XNOR gate demonstrated at 10 and 40Gb/s Loop demonstrated separately at 10Gb/s

3. 3Tyndall, Photonic Systems Group Demonstration of 3-gate system Circulation No. Original data 1 2 3 4 5 6 7 10Gb/s random data Target 1 0 1 0 1 0 Demonstrated at 10Gb/s with arbitrary targets. Example: Circulation No. Original data 1 2 3 4 5 6 7 20Gb/s random data Target 1 0 1 0 …and at 20Gb/s, also with arbitrary targets. Example:

4. 4Tyndall, Photonic Systems Group 3-Gate system at 40Gb/s Circulation No. Original data 1 2 3 4 5 6 7 40Gb/s data Target 1 Circulation No. Original data 1 2 3 4 5 6 7 40Gb/s data Target 1 0 The system works with the target 11111111 (the XOR gate is not required to invert the data) However, the output is poor when the target contains strings of zeros

5. 5Tyndall, Photonic Systems Group Patterning problem inverted XOR gate output measured XOR gate output modelled At 40Gb/s, it was possible to optimise the XOR gate to obtain low patterning (pulse height variation) on the inverted or non-inverted parts of the data signal, but not on both at the same time. A numerical model of the gate showed the same behaviour.

6. 6Tyndall, Photonic Systems Group Experiment to avoid patterning SOA1 SOA2 Data 10Gb/s Target pattern 2 4 1 Output Push Pull 1 Clock SOA1 SOA2 SOA1 SOA2 delay 3 1 3 Initialise Probe with reset Regenerated Loop length (n+1)T Data XOR Target MUX Data 40Gb/s Optical multiplexer Normal experimental arrangement

7. 7Tyndall, Photonic Systems Group Experiment to avoid patterning SOA1 SOA2 Data 10Gb/s Target pattern 2 4 1 Output Push Pull 1 Clock SOA1 SOA2 SOA1 SOA2 delay 3 1 3 Initialise Probe with reset Regenerated Loop length (n+1)T Data XOR Target MUX Optical multiplexer Arrangement for reduced patterning Data/ data 40Gb/s with low patterning Data/ data 10Gb/s Less realistic system

8. 8Tyndall, Photonic Systems Group Probe power problem Placing the multiplexer after the XNOR gate gave a signal with low patterning. Switching at the AND gate in the loop was still poor. Using an arbitrary data signal as the probe in an MZI gate is more demanding than using CW or a regular clock. The probe power needs to be kept low to avoid self switching, which may indicate asymmetry in the MZI. Results in power budget problems in loop. May be resolved with faster SOAs.

9. 9Tyndall, Photonic Systems Group Other outputs Enterprise Ireland have funded the renewal in Ireland and international filing of patent NAT183. They expect commercialisation activity in return “42Gbit/s All-Optical Pattern Recognition” by R.P. Webb, X. Yang, R.J. Manning, G.D. Maxwell, A.J. Poustie, S. Lardenois and D. Cotter was submitted to OFC.

10. 10Tyndall, Photonic Systems Group Conclusions 3-gate pattern recognition system demonstrated with various targets at 10 and 20Gb/s. 40Gb/s operation needs further work.