1. Workshop - November 2011 - Toulouse Paul Brelet TRT paul.brelet@thalesgroup.com Exploration and application deployment on a SoC: efficient application 24/11/2011 1

2. SoCKET Flow Global SoC Req. SoC Architecture Functional validation SW Performance Validation C/C++/ASM Functionality Fonctionnalité + timing Instruction Set Simulator System Requirements Platform Assembly Metrics HLS System Properties Hardware properties Software properties TLM LT TLM AT Software Co-simulation/Co-emulation Silicon Software Execution HLS Traffic generator Metrics IP-Xact SoC Headers generation RTL Software Requirements traceability 2

3. Use case TRT – Description App. Pedestrians detection Algorithm of classification [Viola&Jones] Two steps: Off-line: training by an image database On-line: detection by using the training results Pedestrians tracking in an multi-camera environment Use of the visual covering of the cameras in order to carry out the tracking Utilization of descriptors of forms and/or colors in order to improve the tracking and to manage occlusions 3Workshop - November 2011

4. Thales use case – App. Description Schematic view of the pedestrian detection 4Workshop - November 2011

5. Thales use Case – Architecture Host Architecture details 5Workshop - November 2011

6. Thales use Case – Architecture Accelerator details (Engine) 6Workshop - November 2011

7. Thales use Case – Flow Host Definition: IP-XACT requirements SystemC/TLM generation VHDL generation Architecture Model generation for SPEAR 7Workshop - November 2011

8. Thales use Case – Flow Exploration and Simulation: Architecture SystemC Model generation Architecture Model generation for SPEAR Catch the application on SPEAR C code exists for each SPEAR box (TE) Test of various strategies of application deployment: Exploration of the level of granularity How calculations are paralleled and which divisions data can be apply to minimize the I/O and to reach the performances The accelerators are simulated in SystemC from TE C codes 8Workshop - November 2011

9. Phase 1: Architecture Exploration Library: SystemC2.2 / TLM2.01 Tools: - SPEAR DE, - Magillem: Packager, Platform Assembly, MRV Generator. Validation: Transactional Level. Links: - IPXACT_2_SPEAR Generator (XSLT Script). 9Workshop - November 2011

10. IP-XACT library IPs Template JET Packager MDS PLT Assembly MDS TE Exploration/ Validation Spear Exploration/ Validation Spear TE Spear Application IO API Spear Model SystemC Skeleton client MRV Generator IPXACT 2 SPEAR KO OK Thales Flow: Exploration 10Workshop - November 2011

11. Phase 2: HW Design Level: RTL. Tools: - GAUT: Apply on accelerator engines. - Magillem: Packager, Platform Assembly, Generator Studio. - SPEAR DE: Mapping Validation : Register Level. Links : - Scripts « bash ». 11Workshop - November 2011

12. Template JET HAL SystemC Skeleton client GAUT VHDL Acc. client TE IP-XACT library PLT Assembly MDS Applicatio n Spear Netlister MDS Vhdl FPGA MRV Generator Generator Studio Generic client Validation Thales Flow: RTL Validation 12

13. SPEAR DE Tool SPEAR Flow 13Workshop - November 2011

14. MAGILLEM Tool RTL Level: - Bus interface, components creation, link between components: ditto TLM. VHDL code generation: - Using generics. - The code is readable by an individual. - Inter-connects are taken into account during the VHDL code generation. 14Workshop - November 2011

15. GAUT Tool The C code: - The C code must be very close to VHDL code. - Based on gcc4.3.0 for the “cdfgcompiler” Comparison with commercial tools: - Roccc, ImpulseC. Some troubles during VHDL code generation: - The generated code can be synthesizable but it does not work well in placement/routing. 15Workshop - November 2011

16. Using graphic interface 16Workshop - November 2011

17. Using Bash Script 17Workshop - November 2011

18. VHDL code generation 18Workshop - November 2011

19. DFG Visualization

20. Comparison: VHDL code generation Principe Results Minimum between two images3X3 ConvolutionIntegral Image 20Workshop - November 2011

21. Outlines To propose the projections of the tools for synthesis: - GAUT is an academic alternative compared to industrial tools. - MAGILLEM makes it possible to re-use the IPs blocks. To consolidate the Thales Design Flow. To transfer the Thales Design flow to an operational level. 21Workshop - November 2011

22. Conclusion To re-use the IPs blocks: - Time-saver and productivity in the design of System on Chip. Validity of new Architecture: - Allow to check the information processing applications on the desired architecture. 22Workshop - November 2011

23. Questions? 23Workshop - November 2011