1. ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2009 ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2009 Modeling for Synthesis With VHDL Nitin Yogi 08/21/2009 Fall 09, Aug 211ELEC 5200-001/6200-001 Lecture 3

2. Synthesis Converts behavioral model to structural model Converts behavioral model to structural model --Behavioral model architecture behav of mux is begin p1: process(A,B,S) begin if (S = '0') then Y <= A; else Y <= B; end if; end process p1; end; --Structural model architecture behav of mux is signal Sbar:std_logic begin g1: not port map (Sbar,S); g2: and port map (ASbar,A,Sbar); g3: and port map (BS,B,S); g4: or port map (Y,ASbar,BS); end; A B S Y Synthesis Fall 09, Aug 212ELEC 5200-001/6200-001 Lecture 3

3. Why is Understanding of Synthesis Process Important? Behavioral model architecture behav of ckt1 is begin p1: process(A,B,S1,S2) p1: process(A,B,S1,S2) begin begin if (S1 = '0') and (S2 = '1') then if (S1 = '0') and (S2 = '1') then Y <= A; Y <= A; elsif (S2 = '0') then elsif (S2 = '0') then Y <= B; Y <= B; --else I do not care --else I do not care --what is assigned to Y --what is assigned to Y end if; end if; end process p1; end process p1;end; Synthesis Expected synthesized design Actual synthesized design (oops!!!) Fall 09, Aug 213ELEC 5200-001/6200-001 Lecture 3

4. Why is Understanding of Synthesis Process Important? --Code snippet if (S1 = '0') and (S2 = '1') then Y <= A; Y <= A; elsif (S2 = '0') then Y <= B; Y <= B; --else do not care --else do not care end if; Fall 09, Aug 214ELEC 5200-001/6200-001 Lecture 3 0 1 1 1 1 0 1 1 1 AA - 0 - 0 0 1 0 0 1 BB 1 1 0 1 1 0 0 0 0 B Prev. Stored Value Latch disabled

5. Issues with extra hardware Fall 09, Aug 21ELEC 5200-001/6200-001 Lecture 35 Extra redundant components increase area utilization Extra redundant components increase area utilization More switching activity leading to power loss More switching activity leading to power loss Issues with latches Issues with latches Setup and hold timing violations may prevent correct functioning Setup and hold timing violations may prevent correct functioning Glitches can cause further problems in operation Glitches can cause further problems in operation

6. Why is Understanding of Synthesis Process Important? Corrected behavioral code architecture behav of ckt1 is begin p1: process(A,B,S1,S2) p1: process(A,B,S1,S2) begin begin if (S1 = '0') and (S2 = '1') then if (S1 = '0') and (S2 = '1') then Y <= A; Y <= A; elsif (S2 = '0') then elsif (S2 = '0') then Y <= B; Y <= B; else else --a value is assigned to Y in the “else” clause --a value is assigned to Y in the “else” clause Y <= ‘X’; Y <= ‘X’; end if; end if; end process p1; end process p1;end; Actual synthesized design Thumb rule: Ensure all cases taken care of, using “else” clause for combinational scenarios Fall 09, Aug 216ELEC 5200-001/6200-001 Lecture 3

7. Types of Synthesized Circuits Combinational logic circuits random logic multiplexers decoders Arithmetic functions Sequential logic (registers) synchronous & asynchronous inputs Shift registers Finite state machines Memory synthesis Fall 09, Aug 217ELEC 5200-001/6200-001 Lecture 3

8. Combinational Logic -- Use concurrent assignment or a process. -- All signals referenced in a process must be in the sensitivity list. entity And_Bad is port (a, b: in BIT; c: out BIT); end And_Bad; architecture Synthesis_Bad of And_Bad is begin process (a) -- this should be process (a, b) begin c <= a and b; -- can miss changes in b end process; end Synthesis_Bad; Thumb rule: All signals referenced in the process must be in the sensitivity list Fall 09, Aug 218ELEC 5200-001/6200-001 Lecture 3

9. Multiplexer: Using “case” Statement entity Mux4 is port (i: in BIT_VECTOR(3 downto 0); sel: in BIT_VECTOR(1 downto 0); s: out BIT); end Mux4; architecture Synthesis_1 of Mux4 is begin process(sel, i) begin case sel is when "00" => s <= i(0); when "01" => s <= i(1); when "10" => s <= i(2); when "11" => s <= i(3); end case; end process; end Synthesis_1; Thumb rule: Case statement must be exhaustive Fall 09, Aug 219ELEC 5200-001/6200-001 Lecture 3

10. Multiplexer using concurrent signal assignment architecture Synthesis_2 of Mux4 is begin with sel select s <= i(0) when "00", i(1) when "01", i(2) when "10", i(3) when "11"; end Synthesis_2; Thumb rule: Cover all conditions Fall 09, Aug 2110ELEC 5200-001/6200-001 Lecture 3

11. Multiplexer using an array entity Mux8 is port ( InBus : in STD_LOGIC_VECTOR(7 downto 0); Sel : in INTEGER range 0 to 7; OutBit : out STD_LOGIC); end Mux8; architecture Synthesis_1 of Mux8 is begin process(InBus, Sel ) begin OutBit <= InBus(Sel ); end process; end Synthesis_1; -- if Sel is std_logic_vector, then must convert to integer -- OutBit <= InBus(TO_INTEGER ( UNSIGNED ( Sel ) ) ); Fall 09, Aug 2111ELEC 5200-001/6200-001 Lecture 3

12. Binary decoder function library IEEE; use IEEE.NUMERIC_STD.all ; all use IEEE.STD_LOGIC_1164.all; entity Concurrent_Decoder is port ( enable : in BIT; Din : in STD_LOGIC_VECTOR (2 downto 0); Dout : out STD_LOGIC_VECTOR (7 downto 0)); end Concurrent_Decoder ; Fall 09, Aug 2112ELEC 5200-001/6200-001 Lecture 3

13. Binary Decoder using shifter -- inputs enable, Din (3 bit vector), Dout (8 bit vector) with enable select Dout <= STD_LOGIC_VECTOR(UNSIGNED( shift_left("00000001", TO_INTEGER ( UNSIGNED(Din))))) when '1', "00000000 " when '0', "11111111" when others; -- default for synthesis tool Thumb rule: Cover all conditions using “others” clause Fall 09, Aug 2113ELEC 5200-001/6200-001 Lecture 3

14. ) Decoder (alternate model) process (Din, enable) variable T : STD_LOGIC_VECTOR(7 downto 0); begin if (enable = '1') then T := "00000000"; T( TO_INTEGER ( UNSIGNED(Din ))) := '1'; Dout <= T ; else Dout 0'); end if; end process; Fall 09, Aug 2114ELEC 5200-001/6200-001 Lecture 3

15. Synthesizing arithmetic circuits Synthesis tools will generally recognize overloaded operators and generate corresponding circuits: +,-,*, and abs Special operations: “+1”, “-1”, unary “-” Relational Operators: “=“, “/=“, “ ”, “ =“ Use ranged integers instead of unbound to minimize generated logic. Ex. signal i : integer range 0 to 15; Fall 09, Aug 2115ELEC 5200-001/6200-001 Lecture 3

16. Leonardo restrictions Non-integer data types (std_logic_vector vector) require operator overloading to produce arithmetic circuits (IEEE library packages) Multiply operator “*” will produce a multiplier, but more efficient technology-specific modules may be better. Divide operator “/” only works if dividing by a power of 2, unless using a technology-specific module Fall 09, Aug 2116ELEC 5200-001/6200-001 Lecture 3

17. Adders/ subtracters automatically generated for integer data variable a,b,c: integer; c := a + b; --produces 32-bit adder (signed) variable a,b,c: integer range 0 to 255; c := a + b; --produces 8-bit adder (unsigned) Constant operands result in reduced logic by removing logic due to hard-wired values. Ex:c := a + 5; Thumb rule: Use bounded data-types whenever possible Thumb rule: Use constants in place of variables whenever possible Fall 09, Aug 2117ELEC 5200-001/6200-001 Lecture 3

18. Multiple adder structures z <= a + b + c + d; --3 adders stacked 3 deep z <= (a + b) + (c + d); --3 adders stacked 2 deep Synthesis output Fall 09, Aug 2118ELEC 5200-001/6200-001 Lecture 3

19. Arithmetic with IEEE NUMERIC_STD package library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity Adder4 is port ( in1, in2 : in UNSIGNED(3 downto 0) ; mySum: out UNSIGNED(3 downto 0) ) ; end Adder4; architecture Behave_B of Adder4 is begin mySum<= in1 + in2; -- overloaded '+' operator end Behave_B; Fall 09, Aug 2119ELEC 5200-001/6200-001 Lecture 3

20. Adding n--bit numbers with overflow bit (carry) library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity Adder_1 is port ( A, B : in UNSIGNED(3 downto 0) ; C : out UNSIGNED(4 downto 0) ) ; --C(4) = carry end Adder_1; architecture Synthesis_1 of Adder_1 is begin C <= (‘0’& A) + (‘0’& B); --leading ‘0’to balance # bits end Synthesis_1 ; Fall 09, Aug 2120ELEC 5200-001/6200-001 Lecture 3

21. Sequential adder/subtracter and “accumulator” --result_t, xin, addout are UNSIGNED with addsub select --combinational add/sub addout<= (xin+ result_t) when '1', (xin-result_t) when '0', (others => '-') when others; process (clr, clk) begin --register part if (clr= '0') then result_t '0'); elsif (clk’event) and (clk=‘1’) then result_t<= addout; end if; end process; Fall 09, Aug 2121ELEC 5200-001/6200-001 Lecture 3

22. Simplified “accumulator” model --signal addout eliminated –circuit will be the same process (clr, clk) begin if (clr= '0') then result_t '0'); elsif (clk’event) and (clk=‘1’) then case addsub is when '1' => result_t<= (xin+result_t); when '0' => result_t<= (xin-result_t); when others => result_t '-'); end case; end if; end process; Fall 09, Aug 2122ELEC 5200-001/6200-001 Lecture 3

23. Resource sharing for mutually-exclusive operations process (a,b,c,sel) begin if (sel=‘0’) then z <= a + b ; --either this evaluates else z <= a + c ; --or this evaluates end if ; end process ; Synthesis output Fall 09, Aug 2123ELEC 5200-001/6200-001 Lecture 3

24. Equivalent model process (a,b,c,sel) begin variable tmp: unsigned(0 downto 0) ; begin if (sel=‘0’) then tmp:= b ; --mux will select b or c else tmp:= c ; end if ; z <= a + tmp; --mux output added to ‘a’ end process ; Synthesis output Fall 09, Aug 2124ELEC 5200-001/6200-001 Lecture 3

25. Latches and Flip-flops Latches Latches process (EN, D) --Sensitivity list begin if (EN = ‘1’) then Q <= D ; end if; end process; Flip-flops process (clk) begin if (clk’event and clk= ‘1’) then Q <= D ; end if; end process; Fall 09, Aug 2125ELEC 5200-001/6200-001 Lecture 3

26. Basic format for synchronous and asynchronous inputs process (clock, asynchronously_used_signals) begin if (boolean_expression) then asynchronous signal_assignments elsif (boolean_expression) then asynchronous signal assignments elsif (clock’event and clock = constant) then synchronous signal assignments end if ; end process; Fall 09, Aug 2126ELEC 5200-001/6200-001 Lecture 3

27. Example: register with asynchronous reset and preset process (clock, reset ) begin if (reset = ‘1’) then q <= ‘0’;--reset has precedence elsif (preset = ‘1’) then q <= ‘1’; --asyncpreset elsif (clock’event and clock =‘1’) then q <= d ; --synchronous load end if ; end process; Fall 09, Aug 2127ELEC 5200-001/6200-001 Lecture 3

28. FFs generated from variables: 3-bit shift register example --External input/output din/dout process (clk) variable a,b: bit; begin if (clk’event and clk= ‘1’) then dout<= b; b := a; a := din; end if; end process; --note: a, b used before being assigned new values Synthesis output Fall 09, Aug 2128ELEC 5200-001/6200-001 Lecture 3

29. 3-bit shift register example Unexpected resulting structure process (clk) variable a,b: bit; begin if (clk’eventand clk= ‘1’) then a := din; b := a; dout<= b; end if; end process; --a, b changed before used so values are not stored, so they become “wires”. (Only one flip flop from din -> dout) Synthesis output Fall 09, Aug 2129ELEC 5200-001/6200-001 Lecture 3

30. Finite state machines (FSM) Model states as enumerated type Model “present_state” and “next_state” signals/variables Construct two processes to model FSM One process updates state with next_state One process updates next_state Allow synthesis tool to encode states (binary, one hot, random, gray code, etc.) Consider how initial state will be forced Fall 09, Aug 2130ELEC 5200-001/6200-001 Lecture 3

31. State machine synthesis issues Two-types of FSM models Mealy model: outputs = f ( inputs, state) Moore model: outputs = f ( state ) “case” more efficient than “if-then-elsif…” to test present_state (later builds a priority encoder) Signal assignment consideration Assign outputs & next_state for every case/condition. If an output or next_state is not assigned something under a certain condition in the case statement, the synthesis tools will have to preserve the value with extra latches/flip-flops. Left-most value of enumeration type is default simulation starting value (use reset to initialize real circuit) Fall 09, Aug 2131ELEC 5200-001/6200-001 Lecture 3

32. Moore Model library IEEE; use IEEE.STD_LOGIC_1164.all; entity SM1 is port ( aIn, clk : in std_logic ; yOut : out std_logic ); end SM1; architecture Moore of SM1 is type state is (s1, s2, s3, s4); signal pS, nS : state; pS, begin process ( aIn, pS ) begin -- next state and output functions aIn, pS) case pS is when s1 => yOut <= '0'; if ( aIn = '1') nS <= s4; else nS <= s2; end if; when s2 => yOut <= '1'; if ( aIn = '1') nS <= s3; else nS <= s1; end if; when s3 => yOut <= '1'; nS <= s1; when s4 => yOut <= '1'; nS <= s2; end case; end process; process begin wait until clk = '1'; pS <= nS ; -- update state variable on next clock nS; end process; end Moore ; Moore); Fall 09, Aug 2132ELEC 5200-001/6200-001 Lecture 3

33. Mealy Model library IEEE; use IEEE.STD_LOGIC_1164.all; entity SM1 is port ( aIn, clk : in std_logic ; yOut : out std_logic ); end SM1; architecture Mealy of SM1 is type state is (s1, s2, s3, s4); signal pS, nS : state; pS, begin process (aIn, pS ) begin -- output & nS are functions of aIn and pS case pS is when s1 => if ( aIn = '1') then yOut <= '0'; nS <= s4; else yOut <= '1'; nS <= s3; end if; when s2 => yOut <= '1'; nS <= s3; when s3 => yOut <= '1'; nS <= s1; when s4 => if ( aIn = '1') then yOut <= '1'; nS <= s2; else yOut <= '0'; nS <= s1; end if; end case; end process; process begin wait until clk = '1'; pS <= nS ; -- update state variable on next clock nS; end process; end Mealy ; Fall 09, Aug 2133ELEC 5200-001/6200-001 Lecture 3

34. Memory Synthesis Approaches: Random logic using flip-flops or latches Register files in datapaths RAM standard components RAM compilers Fall 09, Aug 2134ELEC 5200-001/6200-001 Lecture 3

35. Modeling RAM modules library IEEE; use IEEE.STD_LOGIC_1164.all; package RAM_package is constant numOut : INTEGER := 8; constant wordDepth : INTEGER := 8; constant numAddr : INTEGER := 3; subtype MEMV is STD_LOGIC_VECTOR(numOut-1 downto 0); type MEM is array (wordDepth-1 downto 0) of MEMV; end RAM_package; Fall 09, Aug 2135ELEC 5200-001/6200-001 Lecture 3

36. Modeling RAM modules library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.RAM_package.all; entity RAM_1 is port (signal A : in STD_LOGIC_VECTOR(numAddr-1 downto 0); signal CEB, WEB, OEB : in STD_LOGIC; signal INN : in MEMV; signal OUTT : out MEMV); end RAM_1; Fall 09, Aug 2136ELEC 5200-001/6200-001 Lecture 3

37. Modeling RAM modules architecture Synthesis_1 of RAM_1 is signal i_bus : MEMV; -- RAM internal data latch signal mem : MEM; -- RAM data begin process begin wait until CEB = '0'; -- chip enable if (WEB = '1') then -- read if write not enabled i_bus <= mem(TO_INTEGER(UNSIGNED(A ))); elsif (WEB = '0') then -- write enable mem(TO_INTEGER(UNSIGNED(A))) <= INN; i_bus <= INN; else i_bus 'X'); end if; end process; process(OEB, i_bus ) begin -- control output drivers case (OEB) is when '0' => OUTT <= i_bus when '1' => OUTT 'Z'); when others => OUTT 'X'); end case; end process; end Synthesis_1; Fall 09, Aug 2137ELEC 5200-001/6200-001 Lecture 3

38. Resources Material for slides taken from Material for slides taken from Book: Application-Specific Integrated Circuits, Michael J. S. Smith, Addison Wesley Longman, Inc., 1997 Book: Application-Specific Integrated Circuits, Michael J. S. Smith, Addison Wesley Longman, Inc., 1997 Prof. Nelson’s class website for ELEC 5250/6250: Computer-Aided Design of Digital Circuits http://www.eng.auburn.edu/~nelson/courses/elec5250_6250/ Prof. Nelson’s class website for ELEC 5250/6250: Computer-Aided Design of Digital Circuits http://www.eng.auburn.edu/~nelson/courses/elec5250_6250/ http://www.eng.auburn.edu/~nelson/courses/elec5250_6250/ Fall 09, Aug 2138ELEC 5200-001/6200-001 Lecture 3