1. Design review Sampling cell – Buffer - Comparator Ps_TDC v2.0 Herve Grabas - University of Chicago

2. Comparator schematic Ipol = 1uA Dynamic input range from 0 to 1V All Parasitics for comparator4 Report: [x] decoupled C [x] coupled C NetName R sum C sum L /vdd! NA 21.18f 0 /sub! NA 20.44f 0 /net7 NA 2.067f 0 /net42 NA 10.13f 0 /net40 NA 11.14f 0 /net14 NA 6.907f 0 /net033 NA 2.316f 0 /net030 NA 2.212f 0 /gnd! NA 14.28f 0 /Vout NA 4.176f 0 /Vin- NA 6.661f 0 /Vin+ NA 5.944f 0 /Ipolcomp NA 2.252f 0 Number of parasitic instances R: 231 C: 599 L: 0

3. Buffer schematic All Parasitics for buffer4test Report: [x] decoupled C [x] coupled C NetName R sum C sum L /vdd! NA 18.54f 0 /sub! NA 16.39f 0 /net7 NA 4.568f 0 /net42 NA 4.939f 0 /net40 NA 2.299f 0 /net14 NA 1.959f 0 /net043 NA 2.174f 0 /net031 NA 4.349f 0 /gnd! NA 16.43f 0 /avC6 NA 750.9a 0 /Vout NA 9.453f 0 /Vin NA 714.3a 0 /Ipolbuff NA 2.097f 0 Number of parasitic instances R: 173 C: 364 L: 0

4. Sampling cell Write ctrl logic Sampling cell (60pF) Read logic Layout in progress

5. Layout (in progress)

6. Test

7. Test (before layout for the sampling cell but after layout for buffer & comparator)

8. Digitization

9. Parametric simulation