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1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison
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2 Outline ä Microprocessor Technology Trends and Design Issues ä Interconnect delay trends ä Circuit type trends ä Research summary
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3 Microprocessor Design Challenges ä High performance ( > 500 Mhz) ä Low cost (< $100) ä Low power consumption (< 10W mobile) ä More functionality (KNI MMX) ä Shorter time to market (< 18 months) ä Satisfies different market segments (server, sub- $1000) ä Competition ä …. Mission Impossible!
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4 Tentative Class Schedule ä Technology Trends (1 class) ä Interconnect Modeling and Optimization: (1 week) ä basic routing: maze-routing ä wire-sizing, buffer-sizing, buffer-insertion ä Introduction to Verilog (1 week) ä Linear programming and Introduction to C and C++ language (1 week) ä Routing: (2 week) ä Clock routing (0.6 week) ä Global and channel routing, Tree routing (1.4 week) ä Timing Analysis (1 week) ä Delay Characterization, Power Characterization ä PERL and Latch based timing analysis ä Partitioning and Placement (1.5 week) ä Floorplanning (1 week)
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5 Deal With It! ä Higher clock frequencies ä New processes: 0.18 micron, copper ä Architecture level ä Superscalar, super-pipeline, out-of-order execution, speculative execution, EPIC, VLIW, ILP, multi-thread ä Circuit level ä Aggressive dynamic circuits synthesis ä Sizing, parallel re-powering, logic minimization ä Physical Design ä Performance-driven place and route, floorplaning ä Wire-sizing, buffer-sizing, buffer-insertion
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12 Size of Team Explodes
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14 Process Overview ä New process (0.18 um) ä High aspect ratio ä Low sheet rho (resistance) Low- dielectric (capacitance) (3.55 vs. 4.10) ä Good Electromigration property ä 6 metal layers ä M1 tight pitch for density (X-cap) ä M2-M3 middle pitch for density & performance (X-cap) ä M4-M6 high pitch (low resistance) for performance (Inductance) ä Future ä Copper - Less resistance more inductance effect ä SOI - the M1 coupling strange
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15 0.25 Micron, 5 Layer Technology IEDM 96
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16 M6 M5 M4 M3 M2 M1 0.18 Micron, 6 Layer Technology IEDM 99
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17 Gate Delay.v.s. Scaling IEDM 99
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18 Interconnect Resistance Grows Super Linearly IEDM 99
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19 Interconnect Delay Trend IEDM 99
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23 Interconnect Complicated Design Flow Architecture RTL Logic Gate Layout Over tens of iterations!
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24 Signal Integrity A new design challenge CrossCap 1 2 Crosstalk
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25 Inductance effect emerging ä An old clock tree ä Freq domain up to 1Ghz ä PVL and PRIMA with order 16 find the exact ä A newer ckt, a section of power grid ä Has L’s ä PVL and PRIMA with 60th order ä Frequencies more than 0.6 Ghz are not covered Frequency (Ghz)
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26 7072747678 80 -550 -500 -450 -400 Multi-Point PRIMA-34 PRIMA-80 TIM PVL-80 Some MOR result
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29 Model order reduction ä We need efficient tools to analyze the interconnect dominant circuits (power grids, packages etc.) accurately in a reasonable amount of time Promising Model Order Reduction (MOR) techniques Nonlinear Elements Linear Elements Nonlinear Elements Reduced Model
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30 Power Consumption P C V 2 f, where ä C = Capacitance ~ Area ä V = Supply Voltage ä f = Operation Frequency
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31 Power Trend
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32 Supply Voltage Trends
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33 Deal With It! ä Interconnect ä Wire- and Repeater- Sizing ä Repeater Insertion ä Performance-driven noise-aware routing ä New material: Low resistance (Cooper), Low k material (SiN2) ä Gates ä Gate Sizing ä New Circuit Exploration - Dynamic Circuit, Dual Vt ä ….
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34 Standby Power Trend
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35 Threshold Voltage v.s. Supply Voltage
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36 Vt v.s. Delay
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37 Dual Vt circuit High Vt Low Vt
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38 Aggressive circuit styles
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39 Clock delayed and Self-resetting dynamic circuits
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40 Process limitations
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