1. 1 A CMOS 5-GHz Micro-Power LNA 指導教授 : 林志明 教授 學生 : 黃世一 Hsieh-Hung Hsieh and Liang-Hung Lu Department of Electrical Engineering and Graduate Institute of Electrics Engineering National Taiwan University, Taipei, Taiwan, ROC

2. 2 Outline Abstract Introduction Circuit design and analysis Experimental results Conclusion References

3. 3 Abstract LNA for ultra-low-voltage and ultra-low- power application in standard 0.18μm CMOS technology With complement current-reused gain stages 9.2-dB gain and 4.5-dB noise figure at 5 GHz 0.6 V supply voltage and 0.9mW power consumption

4. 4 Introduction CMOS for lower cost and higher level of integration RF, inherently low transconductance Typical CMOS, high bias current and high power consumption, battery lifetime ↓

5. 5 The supply voltage for CMOS RF circuit Feature size ↓ and supply voltage ↓ When supply voltage below 1 V performance ↓

6. 6 LNA of receiver is most power- consumption components Current-reused LNA for NMOS Folded cascode LNA Novel current-reused topology for complementary cascade amplifier

7. 7 Circuit design and analysis A. LNA Topology Current-reused topology Input matching C1,L D1,C2,L D2 Inter-stage matching and dc block 1.V DD between V th and 2V th 2.V D =1/2 V DD

8. 8 B. Small-Signal Characteristics

9. 9 C. Noise and Linearity

10. 10 The micrograph of the fabricated LNA 0.86*1.1mm 2

11. 11 Experimental results

12. 12

13. 13

14. 14 Conclusion A micro-power LNA using a standard 0.18μm CMOS technology BY employing current-reused topology and inter-stage resonance technique 9.2-dB power gain and 4.5-dB noise figure at 5 GHz 0.9mw dc power consumption from an ultra-low supply voltage of 0.6 V

15. 15 References H.-H. Hsieh and L.-H. Lu, “ A CMOS 5- GHz micro-power LNA, ” IEEE RFIC Symposium, pp. 31-34, Jun. 2005

16. 16 Thank You For Your Attention