1. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 10 Input/Output Organization

2. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline Asynchronous data transfersAsynchronous data transfers Programmed I/OProgrammed I/O InterruptsInterrupts Direct Memory AccessDirect Memory Access I/O ProcessorsI/O Processors Serial CommunicationSerial Communication Serial Communication StandardsSerial Communication Standards

3. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Data Transfers

4. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer

5. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Transfer

6. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer with Handshaking

7. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Transfer with Handshaking

8. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Programmed I/O

9. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

10. Example

11. Example

12. Example

13. Example

14. New Instructions

15. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New Control Signals IO differentiates I/O and memory accessesIO differentiates I/O and memory accesses –IO = 1 for I/O access –IO = 0 for memory access

16. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New States and RTL Code

17. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section

18. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section Modify ALUModify ALU

19. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section Modify ALUModify ALU Modify control unit (hard-wired)Modify control unit (hard-wired)

20. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section Modify ALUModify ALU Modify control unit (hard-wired)Modify control unit (hard-wired) Register and ALU sections unchangedRegister and ALU sections unchanged

21. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section Modify ALUModify ALU Modify control unit (hard-wired)Modify control unit (hard-wired) Register and ALU sections unchangedRegister and ALU sections unchanged One new micro-operation: DR  Input PortOne new micro-operation: DR  Input Port

22. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes

23. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC and CLR signals

24. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC and CLR signals

25. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - Memory Read Signal Memory Read = READ ^ IO’Memory Read = READ ^ IO’

26. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts PollingPolling

27. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts IRQ - Interrupt RequestIRQ - Interrupt Request IACK - Interrupt AcknowledgeIACK - Interrupt Acknowledge

28. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts ExternalExternal

29. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts ExternalExternal InternalInternal

30. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts ExternalExternal InternalInternal SoftwareSoftware

31. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Do nothing (until the current instruction has been executed)Do nothing (until the current instruction has been executed)

32. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Do nothing (until the current instruction has been executed)Do nothing (until the current instruction has been executed) Get handler address (vectored)Get handler address (vectored)

33. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Do nothing (until the current instruction has been executed)Do nothing (until the current instruction has been executed) Get handler address (vectored)Get handler address (vectored) Invoke handler routineInvoke handler routine

34. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Vectored Interrupt Hardware

35. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-vectored Interrupt Hardware

36. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiple Non-vectored Interrupts

37. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Daisy Chaining

38. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 IACK in and IACK out

39. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Parallel Priority Interrupts

40. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications

41. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications

42. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupt States

43. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Direct Memory Access

44. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Controller

45. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes Block/Burst ModeBlock/Burst Mode

46. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes Block/Burst ModeBlock/Burst Mode Cycle Stealing ModeCycle Stealing Mode

47. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes Block/Burst ModeBlock/Burst Mode Cycle Stealing ModeCycle Stealing Mode Transparent ModeTransparent Mode

48. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- operations

49. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- operations

50. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications

51. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications

52. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors

53. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations Block transfer commandsBlock transfer commands

54. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations Block transfer commandsBlock transfer commands ALU operationsALU operations

55. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations Block transfer commandsBlock transfer commands ALU operationsALU operations Control commandsControl commands

56. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)

57. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate) start bitstart bit

58. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate) start bitstart bit parity bitparity bit

59. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate) start bitstart bit parity bitparity bit stop bit(s)stop bit(s)

60. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate) start bitstart bit parity bitparity bit stop bit(s)stop bit(s) bit timebit time

61. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication

62. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Synchronous Serial Communication - HDLC

63. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Asynchronous Receiver/Transmitters

64. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 UART Internal Configuration

65. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Request To SendRequest To Send Clear To SendClear To Send Transmission DataTransmission Data Data Terminal ReadyData Terminal Ready Data Set ReadyData Set Ready Received DataReceived Data Data Carrier DetectData Carrier Detect Ring IndicatorRing Indicator GroundGround RS 232C Standard - Signals

66. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection Use RTS, CTS, DTR, and DSR to verify that both devices are activeUse RTS, CTS, DTR, and DSR to verify that both devices are active

67. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection Use RTS, CTS, DTR, and DSR to verify that both devices are activeUse RTS, CTS, DTR, and DSR to verify that both devices are active Use RI to indicate call statusUse RI to indicate call status

68. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection Use RTS, CTS, DTR, and DSR to verify that both devices are activeUse RTS, CTS, DTR, and DSR to verify that both devices are active Use RI to indicate call statusUse RI to indicate call status Use DCD to establish connectivityUse DCD to establish connectivity

69. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection Use RTS, CTS, DTR, and DSR to verify that both devices are activeUse RTS, CTS, DTR, and DSR to verify that both devices are active Use RI to indicate call statusUse RI to indicate call status Use DCD to establish connectivityUse DCD to establish connectivity Use TD and RD to transfer data, and RTS and CTS to coordinate transfersUse TD and RD to transfer data, and RTS and CTS to coordinate transfers

70. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 422 Standard - Signals

71. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard Connects one port to several devicesConnects one port to several devices

72. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard Connects one port to several devicesConnects one port to several devices Transfers data in packetsTransfers data in packets –Token packets –Data packets –Handshake packets –Special Packets

73. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 USB Packet Formats

74. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary Asynchronous data transfersAsynchronous data transfers Programmed I/OProgrammed I/O InterruptsInterrupts Direct Memory AccessDirect Memory Access I/O ProcessorsI/O Processors Serial CommunicationSerial Communication Serial Communication StandardsSerial Communication Standards