1. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Topics n Block placement. n Global routing. n Switchbox routing.

2. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Floorplanning strategies n Floorplanning must take into account blocks of varying function, size, shape. n Must design: –space allocation; –signal routing; –power supply routing; –clock distribution.

3. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Bricks-and-mortar floorplan blocks

4. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Purposes of floorplanning n Early in design: –Prepare a floorplan to budget area, wire area/delay. Tradeoffs between blocks can be negotiated. n Late in design: –Make sure the pieces fit together as planned. –Implement the global layout.

5. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Types of routing n Channel routing: –channel may grow in one dimension to accommodate wires; –pins generally on only two sides. n Switchbox routing: –cannot grow in any dimension; –pins are on all four sides, fixing dimensions of the box.

6. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Channels and switchboxes

7. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Block placement n Blocks have: –area; –aspect ratio. n Blocks may be placed at different rotations and reflections. n Uniform size blocks are easier to interchange.

8. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Blocks and wiring n Cannot ignore wiring during block placement - large wiring areas may force rearrangement of blocks. n Wiring plan must consider area and delay of critical signals. n Blocks divide wiring area into routing channels.

9. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Channel definition n Channels end at block boundaries. n Several alternate channel definitions are possible:

10. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Channel definition changes with block spacing Changing spacing changes relationship between block edges:

11. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR

12. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Channel graph

13. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Channel graph usage n Nodes are channels, edges placed between two channels that touch. n Channel graph shows paths between channels. n Channel graph can be used to guide global routing.

14. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Channels must be routed in order Wire out of end of one channel creates pin on side of next channel: channel A channel B constraint

15. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Windmills Can create an unroutable combination of channels with circular constraints:

16. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR

17. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Slicable floorplan

18. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Slicability property n A slicable floorplan can be recursively cut in two without cutting any blocks. n A slicable floorplan is guaranteed to have no windmills, therefore guaranteed to have a feasible order of routing for the channels. n Slicability is a desirable property for floorplans.

19. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Global routing n Goal: assign wires to paths through channels. n Don’t worry about exact routing of wires within channel. n Can estimate channel height from global routing using congestion.

20. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Line probe routing n Heuristic method for finding a short route. n Works with arbitrary combination of obstacles. n Does not explore all possible paths - not optimal.

21. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Line probe example A A line 1 line 2

22. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Channel utilization n Want to keep all channels about equally full to minimize wasted area. n Important to route time-critical signals first. n Shortest path may not be best for global wiring. n In general, may need to rip-up wires and reroute to improve the global routing.

23. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Switchbox routing n Can’t expand a switchbox to make room for more wiring. n Switchbox may be defined by intersection of channels.

24. Modern VLSI Design 2e: Chapter 7 Copyright  1998 Prentice Hall PTR Routing order and switchboxes Switchboxes frequently need more experimentation with wiring order because nets may block other nets: