1. New Burn In (BI) Methodology for testing of blank Actel 0.15  m RTAX-S FPGAs September 7 th – 9 th, 2005 Minal Sawant Solomon Wolday Paul Louris Dan Elftmann

2. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 2 Introduction  This paper will cover a new approach adopted by Actel to implement the burn in testing of RTAX-S devices using the INCAL state of the art burn in test system  INCAL provided all of the elements needed for a complete operational system including:  Test vector pattern generator which accepts the IEEE 1149.11 SVF (Serial Vector Format) and pattern editor configured to Actel’s requirements for 80MB  Actel worked with INCAL to develop a modified driver board for deep JTAG test stimulus to enable node toggle coverage of the advanced RTAX-S feature set to implement the Dynamic Blank Burn-In (DBBI)

3. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 3 AX and RTAX-S Device Architecture  AX and RTAX-S Device Architecture  Actel's AX and RTAX-S architecture is derived from the highly successful SX-A and RTSX-SU sea-of-modules architecture Figure 2: Axcelerator Family Interconnect Elements Figure 1: Sea-of-Modules Comparison Figure 3: RTAX-S & AX Device Architecture (AX1000 shown)

4. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 4 History of DBBI  EPROM Based System  The Actel RTSX-S product is processed in an EPROM based burn in oven with bulk power supply for biasing  The burn in systems which have been used for RTSX-S burn in were sufficient for the device features and densities  System capabilities  Systems have a capability of 48 vector drive channels  A maximum vector depth of 8 Megabits  A typical EPROM that Actel uses is a ST Microelectronic M27C1001 (128Kb x 8) 1 Megabit UV EPROM  Vector clock frequency is 512 KHz  Four different voltage supplies  Manual operation required for setting voltage levels, temperature, power-up and power-down sequencing  No constant monitoring of the voltage, current, temperature or Device Under Test (DUT) output signals

5. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 5 History of DBBI  Limitation of EPROM for RTAX-S and the switch to INCAL  Several limitations exist in the EPROM based burn in system  No system control  No system voltage and current monitoring capabilities  No DUT monitoring capabilities  Limited vector depth of 8 Megabits  Distinct advantages of INCAL Tracer I160 Burn in system over traditional burn in methodologies  Automated upload sequence of lot  Constant monitoring of the system, DUT input and DUT output signals during burn in  Deep vector capability (>200 Megabit)  Existing INCAL Tracer I160 Burn in system had a limitation in vector depth  Actel worked closely with INCAL to add the deep vector capability to the INCAL Tracer I160 driver board  Software support added to translate Teradyne J750 ATP test vector format to Serial Vector Format (SVF) format  Software support added for SVF The Serial Vector Format was developed as a vendor-independent method to represent JTAG (IEEE 1149.1) test patterns in ASCII (text) files

6. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 6 INCAL Tracer I160 Burn In System Features  INCAL System Overview  The INCAL Tracer I160 Burn In System is fully automated for control and monitoring at the system and DUT level  The system capabilities include  System controlled by Windows 32 bit computer operating system  Logging of system events  Logging of lot history  Four power zones enables different products to be run simultaneously under controlled thermal stress conditions  The system monitors temperature, run time and voltage levels Figure 4: INCAL Tracer I160 Burn In System Photo

7. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 7 INCAL Setup File  Setup File -- Defines test conditions  Bias levels  Over voltage level  Under voltage level  Current limit  Power up & power down sequence  Vector data file  Burn In Board serial file  Burn In duration  Temperature set point  Temperature trip points  DUT monitoring definition  Sign of life  Vector compare  Frequency  Voltage Figure 5: INCAL Tracer I160 Burn In System Setup File Editor

8. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 8 INCAL I-Scope Signal Monitor Feature  I-Scope Signal Monitor  I-Scope signal monitor is a valuable tool for debugging or verifying vectors  The signal monitor is used for:  Signal frequency measurement  Pulse width measurement  Visual inspection of vector data  Eight signals can be scoped & displayed on the screen  Monitoring is possible for each burn in board  Monitoring can be done at any time during the process Figure 6: INCAL Tracer I160 Burn In System I-Scope Signal Monitor Window

9. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 9 INCAL DUT Status Window  DUT Status window  Feature available at any time during the process  Three window sections  Voltage & Alarm Status  Voltage set point  Voltage level on BIB  Power supply alarm status  Driver board alarm status  Driver Status  Driver board configuration and run status  DUT Status array monitor  The array represents the physical burn in board positions  DUT Status Color definitions Green = Pass Red = Fail White = Empty Black = Bad socket DUT Status Voltage & Alarm Status Driver Status Figure 7: INCAL Tracer I160 Burn In System DUT Status Window

10. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 10 Burn In Of Actel FPGA’s  Burn In of Actel FPGAs  During blank device electrical testing, Actel devices are subjected to controlled voltage stress to the maximum operating conditions  Voltage stress testing of semiconductor devices is a much more effective screen than a temperature burn in  Actel takes advantage of the testability features of its FPGA products to provide effective dynamic burn in of blank devices  Burn in is required for all MilStd-883 “B” and “E” flow products  MIL-883E Method 1005, allows several types of burn in screens, which can be divided into two categories:  Dynamic Blank Burn In (DBBI)  Static Blank Burn In (SBBI)

11. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 11 Goal Of Burn In  DBBI  Dynamic burn in applies AC signals to device inputs  These signals are selected so that the device receives internal and external stresses similar to those it would experience in a typical application  A properly designed dynamic burn in can effectively stress inputs, outputs, and internal circuits  Actel performs DBBI for four main reasons:  Stress un-programmed antifuses  Stress internal CMOS logic  Stress internal SRAM blocks  Stress I/Os  SBBI  Static burn in applies DC voltage levels to the pins of the device under test with the device powered up  Static burn in can be an effective screen for mobile ionic contamination failure modes, which affect device inputs or outputs  Effective design of seal ring barriers and device passivation makes this type of contamination highly unlikely

12. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 12 Device Feature Coverage  General Description  The RTAX-S architecture is such that test and stimulation of internal logic elements as well as the external I/Os is possible through the IEEE 1149.1 Joint Test Action Group (JTAG) interface  The expanded vector depth capability of the INCAL Tracer I160 Burn In system enables Actel to run patterns with out limitations on pattern size for RTAX-S products  The burn in patterns are the same patterns used during Automated Test Equipment (ATE) testing of blank devices to test for functionality and apply stress  This ensures coverage of all the device features during burn in  The functional test patterns are monitored for functionality of each device during burn in real time Device Pattern file size (Kilobytes) Length/Depth (Vectors) RTAX250S 14,6219,211,536 RTAX1000S 47,67430,040,480 RTAX2000S 83,33152,509,680 Table 1: RTAX-S Burn In pattern sizes

13. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 13 List of Burn In Tests  Burn In Tests  General description of patterns used for the blank burn in and whether monitoring is done for each test Table 2: List of RTAX-S Burn In tests

14. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 14 Burn In Tests  Burn in for the DBBI test is run at a clock frequency of 2 MHz  The burn in tests are done sequentially as shown in Figure 8 with the duration of one test cycle represented as “T”  For one test cycle (T) each test gets executed once  Estimates for the number of times each test gets executed during a 160 hour burn in for the B-flow process are listed in Table 3 Device T (seconds) Execution Count RTAX250S 4.5 128,000 RTAX1000S 15 38,400 RTAX2000S 26 22,153 Figure 8: RTAX-S Dynamic Blank Burn In pattern sequenceTable 3: RTAX-S Dynamic Blank Burn In pattern times

15. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 15 Detailed Description  Bin circuit test  The binning circuit on RTAX-S consists of two ring oscillators that clock a counter  The path delay of the first ring oscillator is dominated by the CMOS transistor speed  The path delay of the second ring oscillator includes six antifuses programmed immediately after assembly  The second path also includes un-programmed antifuses to emulate antifuse capacitive track loading  This test is done by enabling the charge pump and loading an instruction through the JTAG interface  Once enabled the two bin circuit paths are exercised by toggling the TDI pin  TDO pin will toggle, but is not monitored during burn in

16. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 16 Antifuse Stress  Antifuse Stress Test Circuit  Antifuse stress is done using the same Direct Access (DA) and Programming Voltage (PV) devices used during programming Figure 9: RTAX-S Antifuse Stress Test Circuit

17. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 17 Antifuse Stress  Cross Antifuse  Cross Antifuse Stress patterns switch the voltage across the cross antifuses in the FPGA  This is done using the same DA and PV devices used during programming  During this test, all cross antifuses, clock antifuses and input class antifuses are stressed  I/O Antifuse Stress  I/O configuration antifuses are stressed in alternate directions  This is done via separate patterns in a manner similar to the cross antifuse stress patterns  During this test the I/O bank configuration antifuses are also stressed  Horizontal and Vertical Antifuses  These two patterns apply a stress pattern to the horizontal and vertical antifuses in alternate directions  These antifuses are utilized to extend horizontal and vertical segments  This is done using a similar methodology as the cross antifuse stress patterns with specific adjustments for the horizontal and vertical antifuse addressing scheme

18. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 18 I/O Test  Clock Tests  Two patterns are used for this test to stimulate both the routed and the hardwired clock trees  The output stage of the clock multiplexers is toggled during these patterns  I/O test  Three patterns are used to toggle the different I/O standards  The aim of single ended I/O stress is to toggle all single-ended I/O input and output buffers in the device  This is done using the JTAG Boundary Scan Register (BSR)  All I/O pads including un-bonded I/O pads get exercised  The I/O pads are driven through states “high”, “tristate” and “low” levels during burn in  These states are driven on output buffers and read back at the input buffers as shown in Figure 10 on next slide

19. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 19 I/O Stress  I/O test diagram  The I/O test is done by driving the output buffer through the OUTBSR and reading the value at the INBSR  The V REF and differential I/O testing is done by setting configuration MUXs to select either the V REF I/O input or the I/O pad input and going through the differential amp Figure 10: Simplified Diagram of I/O Circuit

20. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 20 Core Logic Module Tests  Core logic modules are exercised and monitored during burn in with the Core Logic Module Tests  Combinatorial logic  Sequential logic  Buffer  The Buffer module takes a regular routed signal from the horizontal channel in the same row or the row to the North and drives its own Output-track  TX and RX  The TX module provides transmission capability to the horizontal and vertical highway channels  The RX module receives a signal from a horizontal highway channel in the same row or a vertical highway channel in the same SuperCluster column and transfers it to its own Output track for distribution with regular routing means  Carry chain  Logic modules in a column are linked into a carry-chain running from North to South  They provide high-speed propagation of carry logic for ripple style arithmetic functions  Carry-connect module utilizes a hardwired signal path which does not require a programmable interconnection

21. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 21 Core Logic Module Test Example  The module test is done one row at a time using the programming voltage (PV) read-back method  Input is provided by turning on the Input Direct Access (IDA) devices and applying the stimulus on Horizontal Programming Voltage Drivers (HPV)  The output signal gets captured by turning on the Output Direct Access (ODA) device and reading the signal via the VPV  The values captured in the VPV are shifted out through the JTAG interface to the TDO output pin Figure 11: Core Logic Module Test Diagram

22. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 22 Single Event Upset (SEU) Enhanced Sequential Module  The SEU enhanced sequential module shown in Figure 12 has additional circuitry (not shown) to inject faults into each latch to verify the voter gate circuitry during sequential logic tests  This test is monitored during burn in Figure 12: SEU Enhanced Sequential Module

23. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 23 SRAM/FIFO Test  SRAM/FIFO test  There are four Built In Self Test (BIST) tests designed to test the FIFO counters for SRAM cascaded configurations  All blocks on the chip are simultaneously tested  FIFO logic for each block is cycled through the complete addressing sequences for all possible configuration depths  Test Methodology  There are three sections of Cyclic Redundancy Code (CRC) registers in each SRAM/FIFO block  Each section collects the test response from a specific type of circuit  Shifting control data into the SRAM/FIFO blocks through the tap port operates the BIST  The CRC signature result from running the BIST test is shifted out and compared against expected value from simulation

24. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 24 Burn in System Comparison FeatureEPROM based System INCAL Tracer System Memory depth 8 Megabit200 Megabit Number of Drive Channels Number of monitor channels 48 0 3696* 160* 64 64* 0* Computer controlledNoYes Automated lot sequence (Bias, Vectors & Temperature) NoYes Constant system monitoring (Voltage, Current & Temperature) NoYes Constant DUT monitoring during burn inNoYes Vector debugging during burn inNoYes System status during burn in (Driver Board, Power Supply & System Alarms) NoYes Logging of system events and lot reportsNoYes Table 4: Burn in System Comparison * Standard INCAL Tracer System Driver Board (non-SVF)

25. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 25 Conclusion  Thru partnership with INCAL Technology, Inc. Actel was able to leverage industry standards (IEEE 1149.1) to develop a system that can be used for devices and technologies beyond Actel FPGAs  Actel has successfully implemented a new burn in methodology for the Axcelerator architecture  Significantly increased visibility into burn in operations  Complete system control  Constant monitoring of DUT functionality  Constant monitoring of voltage, temperature and current  System enables quicker turn around time for continuous enhancements of test coverage  ATE test patterns are easily converted to SVF format  Expanded vector depth capability enables Actel to run patterns with fewer limitations on pattern size  Ability of real time debug during burn in  Logging of system events and lot status

26. Appendix Axcelerator Architecture

27. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 27 Embedded Memory  Each core tile has either three (AX250 & RTAX250S) or four (All other devices) embedded SRAM blocks along the west side  Each variable-aspect-ratio SRAM block is 4 Kbits in size  Available memory configurations are:  128 x 36, 256 x 18, 512 x 9, 1K x 4, 2K x 2 or 4K x 1 bits  The individual blocks have separate read and write ports that can be configured with different bit widths on each port  For example, data can be written in by 8 and read out by 1  The embedded SRAM/FIFO blocks can be cascaded to create larger configurations  The embedded SRAM blocks can be initialized at power up via the device JTAG port (ROM emulation mode)

28. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 28 I/O Logic  The Axcelerator family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages with its bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V.  Axcelerator FPGAs support 14 different I/O standards (single-ended, differential, voltage-referenced)  The I/Os are organized into banks, with eight banks per device (2 per side)  The configuration of these banks determines the I/O standards  An I/O Cluster includes two I/O modules, four RX modules, two TY modules, and a Buffer (B) module  Each I/O module has an input register (InReg), output register (OutReg) and enable register (EnReg) Figure 13: AX & RTAX-S I/O Cluster Block Diagram

29. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 29 Routing and Resources  The AX & RTAX-S hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together  The level 1 routing structures -- Figure 14 on next slide  In and between SuperClusters are three local routing structures:  FastConnect FastConnects provide high-performance horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it Only one programmable connection is used in a FastConnect path  CarryConnect routing CarryConnects are used for routing carry logic between adjacent SuperClusters They connect the FastConnect output (FCO) of one 2-bit, C-cell carry logic to the FastConnect Input (FCI) of the 2-bit, C-cell carry logic of the SuperCluster below it CarryConnects do not require an antifuse to make the connection  DirectConnect DirectConnects provide the highest performance routing inside the SuperClusters connecting the C-cell to the adjacent R-cell DirectConnects do not require an antifuse to make the connection

30. New BI Methodology MAPLD 2005 / #239Sawant, Wolday, Louris, Elftmann 30 Routing and Resources (con’t)  The level 2 routing structures -- Figure 14  The next level contains the core tile routing  In SuperClusters within a core tile vertical and horizontal tracks run across rows and columns  At the chip level, vertical and horizontal tracks extend across the full length of the device  north-to-south and east-to-west  These tracks are composed of highway routing that extend the entire length of the track as well as segmented routing of varying lengths Figure 14: AX & RTAX-S Routing Architecture