1. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Introduction to Electronics in HEP Experiments Philippe Farthouat CERN

2. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Outline 2 Detector Analog To Digital Conversion Data Acquisition & Processing Analog Processing On-detector Or Off-detector  Analog processing  Analog to digital conversion  Technology evolution  Off-detector digital electronics

3. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Analog to Digital Conversion  Data from a detector needed in digital form for additional processing, storage and later analysis  Analog to Digital  Three type of data  Signal higher than a given threshold  1-bit ADC or discriminator  Amplitude measurement  e.g. what is the value of a signal after the preamplifier and shaper  N-bit ADC  Time measurement  What is the time between two signals (e.g. time of flight)  What is the arrival time of a signal (e.g. drift time in a chamber)  What is the duration of a signal (e.g. how long time is a signal above the threshold [TOT|)  Time to digital conversion (TDC) 3

4. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Time to Digital Conversion  Introduction  Discriminator  Definition  Time walk  Slewing time  Double-threshold discriminator  Constant fraction discriminator  Different types  Time to Amplitude Converter (TAC)  Wilkinson  “Direct” measurement  Tests 4

5. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 What is to be measured?  Time difference between physics signals  Time of flight between two scintillator hodoscopes  Time difference between a physics signal and a logic signal  Time difference between a wire chamber signal and the beam crossing signal  Before feeding a TDC, a physics signal must be transformed in a logic signal in phase with it  Using normalised electrical levels (e.g. NIM, TTL, ECL, LVDS)  This is the role of the discriminator 5

6. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Discriminator  Input = analog signal  Output = digital signal  After a fixe delay if possible  If the signal exceeds a threshold  A discriminator  high gain amplifier 6

7. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Example 7

8. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Time walk  Often homothetic signals (e.g PM outputs):  constant rise time  variable amplitude  The phase of the output signal of a discriminator will depends on the signal amplitude  Time walk  Example  10 ns rise time, 10-1000 mV input, 50 mV threshold  Time walk about 10 ns 8 Input Output

9. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Slewing time  Assuming a “zero” rise time signal  Time walk = 0  Still an effect of amplitude because:  The discriminator requires a minimum overdrive  The transit time changes for small overdrives 9 AD 8611 CMP401

10. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Double threshold  Low threshold to give the timing information  Minimise time walk  Noise 10 - + - + Input High-Thr Low-Thr Clk D Reset Q Delay Output Inputs Comparators Outputs Thresholds

11. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Constant fraction (1)  Homothetic signal  V(t) = A * F(t)  k * V(t) - (t-t0) V(t-t0)  Null for t, independent of A 11 Crossing point independant of amplitude

12. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Constant fraction (2)  Timing given by the crossing point  k * V(t) = (t-delay) V(t-delay)  k is the fraction  Very good performances: no time walk 50mV-1V  Limitations  Offset of the comparator  Noise  Slewing time of the comparator 12 - + - + Input High-Thr Clk D Reset Q Delay Output Delay Fraction

13. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Time to amplitude converter  Very good resolution can be achieved (a few ps) 13 Start Set Reset Q Stop C I ADC - +

14. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Wilkinson encoder  Resolution and conversion time function of the clock frequency  Old modules: 25 ps resolution for 100 ns dynamic range 14 I1 Start Set Reset Q Stop C - + Enable N-bit Output Oscillator Clk Counter V I2 << I1 Start conversion Set Reset Q

15. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Direct measurement  Count number of clock cycles between 2 signals  Requires high speed clock to obtain good resolution  Possible with the new technologies  Is even implemented in FPGA (Programmable logic)  Requires some additional interpolation techniques to get high precision  Presentation of a CERN design  High Precision General Purpose TDC (HPTDC) (J. Christiansen etal)  32-channel TDC  Bin 100, 200, 400 or 800 ps  Dynamic range about 100 ms 15

16. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 HPTDC  Based on a 40 MHz Clock  Measurement relative to the clock 16

17. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 PLL and DLL  Phase Lock Loop (PLL) provides clock multiplication and maintain the phases of the clocks  Delay Lock Loop (DLL) provides 32 clocks delayed by a constant amount  Delay: 780 ps, 390 ps, 195 ps, 100 ps depending on the used clock  Used to interpolate between two main clock hits (vernier) 17

18. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 18 Coarse time count  A 15-bit counter gives the coarse timing of the hit with respect to a RESET signal (which could be the START in a start-stop configuration)  Two counters are implemented to take into account the asynchronous nature of the signal  The position of the hit within the clock period is used to select the good one

19. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 19 Tests and measurements  Timing resolution  Start-Stop without jitter  Integral Linearity  Delay scanning  Differential Linearity  Non-correlated Start-Stop  Hit frequency histogramming

20. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Introduction to Analog to Digital Conversion  Introduction  Conversion errors  Different types of A-to-D converters  Trends in our applications 20

21. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Introduction to Analog to Digital Conversion  Alterations of the signal:  Signal is sampled at given instants (sampling time)  Continuous amplitude is encoded in a limited number of binary word, i.e. a binary word represents an interval of amplitude (quantization) 21 Time Binary code 00001 00010 00011 00100 00101 …..

22. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Introduction to Analog to Digital Conversion  Restitution of the signal with a DAC (Digital-to-Analogue Converter)  Both aspects of the digitisation (Time Sampling and Amplitude Quantization) have to be considered 22 Time Amplitude

23. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Resolution  Relationship between quantization error, number of bits, resolution: 23 Binary code …00000 …00001 …00010 …00011 …00100 ….. Amplitude interval : LSB=A/2 n Ex : 8 bits ADC, 1V Full Scale Amplitude  Resolution (LSB) = 1/2 8 = 3.9 mV (0.39%) A = maximum amplitude n = number of bits Max Quantization error : Q = +/- LSB/2 (ideal) Quantization noise : …11111

24. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Dynamic range  Ratio between the minimum and the maximum amplitude to be measured  e.g. calorimeter signal 10 MeV to 2 TeV gives a 2 10 6 dynamic range  In case of a linear system the dynamic range is related to the number of bits (and hence the resolution)  an 8-bit linear ADC has a 256 dynamic range  In case of large dynamic range, linear systems cannot be used:  A calorimeter signal in HEP for which the dynamic range could be as high as 2 10 6 would require a 21-bit linear ADC  Some non-linearity is then introduced and there is distinction between dynamic range and resolution. Do not confuse them!  n-bit resolution  N-bit dynamic range (N>n)  example:  12-bit resolution for a 16-bit dynamic range means that a signal in the range 1-65000 is measured with a resolution of 0.02% 24

25. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Resolution & Speed  There is a trade-off between sampling rate and number of bits  The choice of an ADC architecture is driven by the application 25 Speed (sampling rate) Flash Sub-Ranging Pipeline Successive Approximation Ramp Sigma-Delta GHz Hz 6 22 bipolar CMOS Discrete Power >W <mW Number of bits

26. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 ADC transfer curve  Ideal ADC  Errors  Offset  Integral non-linearity  Differential non-linearity 26

27. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Integral linearity  Non linearity: maximum difference between the best linear fit and the ideal curve 27 Non Linearity

28. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Analog Input Code +0.5LSB DNL -0.6LSB DNL Differential non-linearity  Least Significant Bit (LSB) value should be constant but is not 28  Easy way of seeing the effect  Random input covering the full range  Frequency histogram should be flat  Differential non-linearity introduces structures

29. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 ADC errors : Missing code, monotonicity  Other conversion errors :  non-monotonic ADC  Missing code 29 Missing code Non-monotonic

30. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Effective number of bits  Effective number of bit of an n-bit ADC  n’ giving the correct SNR  Example: AD9235 12-bit 20 to 65 MHz  SNR = 70 dB  Effective number of bits = 11.4 30  (x) q  An n-bit ADC introduces a quantization error  Encoding a signal x= (A/2) sinwt with A being the full scale will give an error  Signal to Noise Ratio

31. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Types of ADC  Flash ADC & Subranging Flash ADC  Pipeline ADC  Successive Approximation ADC  Ramp ADC  Sigma-Delta 31

32. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Flash ADC  Signal amplitude is compared to the set of 2 n references  Direct “thermometric” measurement with 2 n -1 comparators  Typical performance:  4 to 10 bits (12 bits rare)  Up to GHz (extreme case)  High power (2 n comparators) typ. Watts 32 Sampling

33. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Sub-ranging Flash ADC  Typical performance:  4 to 10 bits  Up to 100 MHz  Less power, but difficult analogue functions (sample and hold, subtraction, DAC) 33 4-bits + 4-bits sub-ranging flash needs 30 comparators (instead of 255 for 8-bits flash) Required  Half-Flash ADC  2-step Flash ADC technique  1st flash conversion with 1/2 the precision  Residue calculation (1st flash conversion result reconstructed with a DAC and subtracted from signal)  Residue flash conversion

34. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Pipeline ADC  Pipeline ADC  Input-to-output delay = n clocks for n stages  One output every clock cycle (as for Flash)  Saves power (N comparators)  Typ. 12 bits 40MHz 200mW 34 S&H Comparator1-bit DAC - X 2 1-bit S&HStage 1Stage 2Stage 3Stage N Time Adjustment & Digital Error Correction 1-bit N-bit Input ………… Sampling

35. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Successive approximation  Compare the signal with an n-bit DAC output  Change the code until  DAC output = ADC input  An n-bit conversion requires n steps  Requires a Start and an End signals  Typical conversion time  1 to 50 µs  Typical resolution  8 to 12 bits  One comparator  Power  10 mW 35 S&H Sampling Input

36. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Ramp ADC  Start to charge a capacitor at constant current  Count clock ticks during this time  Stop when the capacitor voltage reaches the input  Very slow, can reach very high resolution (1s, 18 bits) with some further tricks (dual slope conversion) 36 - + C R S Enable N-bit Output Q Oscillator Clk Counter Start Conversion Vin Counting time (What’s used in digital multimeter) S&H Input

37. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Over-sampling ADC  Assuming the error is a white noise, its power spectral density is flat within the range [–fs/2,fs/2] (fs being the sampling frequency)  If fs/2 is higher than the maximum frequency f0 of the signal, then after filtering the quantization noise left in the signal frequency band (<f0) is : 37  (x) q -fs/2+fs/2 f |  (f)| fs/2

38. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Over-sampling ADC (cont)  The signal to noise ratio when encoding a signal with maximum frequency f0 with sampling at fs  Hence it is possible to increase the resolution by increasing the sampling frequency and doing the proper filtering  Example :  an 8-bit ADC would become a 12-bit ADC with an over-sampling factor of 250 (!)  But it is not an effective mean of increasing the resolution, because the 8-bit ADC must meet the linearity requirements of a 12-bit ADC 38

39. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Sigma-Delta ADC  Over-sampling ADC using a feedback loop to further reduce noise in the low-frequency range have been developed : the most common today is the Sigma-Delta Converter  The feedback loop provides a further “noise shape” with effective noise reduction in the signal frequency band 39 1-bit ADC 1-bit DAC - Input Output 1rst Order Sigma-Delta Modulator

40. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Sigma-Delta ADC  This architecture is highly tolerant to components imperfections  With strong Noise shaping and high linearity capability, Sigma- Delta modulators are capable of very high resolution (up to 24 bits)  However some other limitations may appear and several complex architectures are derived from the “basic” schema 40 1-bit ADC 1-bit DAC - Input Output 1rst Order Sigma-Delta Modulator

41. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Sigma-Delta ADC  The output of this modulator is a digital stream, whose average value is an approximation of the input signal.  Quantization error in case of a first-order S-D converter: 41 1-bit ADC 1-bit DAC - Input Output 1rst Order Sigma-Delta Modulator (Over-sampling ratio OSR=f s /2f 0 )

42. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Sigma-Delta ADC (cont)  The signal to noise ratio when encoding a signal (A/2) sinwt, with A being the full scale, will be  Gain of 1.5 bits per each doubling of OSR  OSR = 2400 to have a 16-bit ADC  Higher orders sigma-delta are implemented to reduce OSR  Examples (Analog Devices)  16-bit, 2.5 MHz  24-bit, 1kHz 42

43. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Shannon Theorem  A signal x(t) has a spectral representation |X(f)|; X(f) = Fourrier transform of x(t)  A signal x(t) after having been digitised at the frequency fs, has a spectral representation equal to the spectral representation of x(t) shifted every fs  If X(f) is not equal to zero when f > fs/2, there is spectrum overlapping  Shannon theorem says that x(t) can be reconstructed after digitisation if the digitising frequency is at least twice the maximum frequency in x(t) spectral representation  This is mathematical only as it supposes perfect filtering 43

44. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Example (1)  “Typical” physics pulse  100 ns rising and falling edge  Effect of a digitisation at 10 MHz and 20 MHz 44

45. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Example(2)  100 ns square pulse  Digitisation at 10 MHz and 20 MHz 45

46. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Using sampling ADC  Don’t forget to make a frequency analysis of the signal  Any spectrum overlapping introduces noise  Take into account the effective number of bits  Filtering is necessary  Before digitisation (analog) to cut the input signal frequency spectrum  After digitisation (digital) to extract the signal frequency spectrum and to compensate the effect of digitisation over a finite time window 46 -T0 +T0 1/2*T0

47. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Trends in digitisation  We see more and more the digitisation happening “as soon as possible” in the readout chain  Minimises the difficult problems of handling analog data  Noise  Needs for keeping data for a while before a trigger decision arrives  e.g. in LHC experiments, data stored every 25ns (Bunch crossing period) and trigger decision after sevral µs  Complex filtering for noise optimisation, tails cancelation, … can be done in a digital way in a very efficient and flexible way 47

48. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Examples of early digitisation  ALICE TPC readout chip (ALTRO)  16 ADC 10-bit 20MHz digitised the preamplifier-shaper output  Digital filtering implemented in the chip  CMS electromagnetic calorimeter  12-bit 40MHz ADC  Dynamic range extended with a 4-gain shaper  4 ADC per channel 48 CMS Calorimeter

49. philippe.farthouat@cern.chIntroduction to Electronics Summer 2009 Future projects with early digitisation  Super ALTRO for reading out a Linear Collider TPC  32 or 64 complete channels including the preamplifiers, the 10- bit 10MHz ADC and the digital data processing  Upgrade of the ATLAS calorimeters for sLHC  Coding at 40 MHz, 14–16-bit  About 200000 channels  For all these applications, very low power ADC are needed  That’s now possible thanks to the evolution of technologies 49