1. Research of long distance clock distribution system Université Libre de Bruxelles (IIHE) Yifan Yang, Kael Hanson, Aongus Ó Murchadha, Thomas Meures, Michael Korntheuer

2. SEP 2012 TWEPP2 OVERVIEW Askaryan Radio Array background Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. Fixed latency link implementation. Conclusion and future plan.

3. SEP 2012 TWEPP3 Askaryan Radio Array background Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. Fixed latency link implementation. Conclusion and future plan.

4. SEP 2012 TWEPP4 37 stations Spacing: 2 km Depth under ice surface: 200 m Surface coverage: ~160 km 2 Ice thickness below: ~3000 m Each station: 16 + 4 sub-firn antennas (sensitive between 250 and 800 MHz): 8 vertically polarized 8 horizontally polarized 4 calibration pulsers (v-pol + h-pol) X surface antennas Askaryan Radio Array

5. SEP 2012 TWEPP5 Askaryan Radio Array Current ARA uses analog optical fiber Easy, COTS (commercial off-the-shelf) item 1 antenna = 1 fiber => 4 fibers per hole slightly high power draw price > 10 kEUR per station 4 ADC board on surface controlled by single processor board Digital system Custom designed 4 antenna =1 fiber => 1 fiber per hole Half the price Extended communication system 1 ADC board downhole controlled by one FPGA board 50 ps skew stability is required in one station 800Mbps data rate

6. SEP 2012 TWEPP6 Askaryan Radio Array background Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. Fixed latency link implementation. Conclusion and future plan.

7. SEP 2012 TWEPP7 Clock embedded in data self-clocking signal

8. SEP 2012 TWEPP8 GTP To SFP From SFP Recovered clock is synchronized with transfer clock but with larger jitter

9. SEP 2012 TWEPP9 SI5368 Generates any frequency from 2 kHz to 945 MHz Ultra-low jitter clock outputs with jitter generation as low as 300 fs rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth Footprint compatible Interface compatible with on-surface processor board

10. SEP 2012 TWEPP10 Evaluation board and measurement setting IRS2 Control module System clock After switching to recovered clock, a synchronized link is established Spartan 6 lx45t with 4 GTPs SI5368

11. SEP 2012 TWEPP11 Clock and data measurements

12. SEP 2012 TWEPP12 Latency measurements Before clock switching After clock switching

13. SEP 2012 TWEPP13 Clock skew measurement

14. SEP 2012 TWEPP14 Askaryan Radio Array background Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. Fixed latency link implementation. Conclusion and future plan.

15. SEP 2012 TWEPP15 Latency uncertain from GTP

16. SEP 2012 TWEPP16 Latency uncertain from GTP

17. SEP 2012 TWEPP17 Latency uncertain from jitter cleaner Fixed phase difference between input and output of the jitter cleaner is also needed to establish a fixed latency link. Cdce62005 and LMK03200 both are used in new evaluation board. IRS2 Control module System clock

18. SEP 2012 TWEPP18 New evaluation board and measurement setting Spartan 6 lx45t with 4 GTPs Cdce62005(fixed delay) Lmk03200(0 delay)

19. SEP 2012 TWEPP19 Mean (ps) Std dev(ps) P-p (ps) Popul- ation 1934.469.7717105.371.375 M 2925.4310.10099.2391.25M 3908.410.001105.681.25M 4934.9810.047103.641.25M Clock skew measurement

20. SEP 2012 TWEPP20 Askaryan Radio Array background Clock distribution over optical fiber based on low cost FPGA and jitter cleaner. Fixed latency link implementation. Conclusion and future plan.

21. SEP 2012 TWEPP21 Conclusion and future plan Achieved: Clock distribution over optical fiber 50ps skew stability achieved Latency of the link is kept in a certain range after power cycle on both direction Things to do: Long term, long distance, low temperature experiments Automatic calibration Remotely firmware upgrade System optimum

22. SEP 2012 TWEPP22 Thank you!

23. SEP 2012 TWEPP23 backup

24. SEP 2012 TWEPP24 Clock separate with data transfer 250 meters standard cat5 cable